Concept renderPDM uses one clock, and each data line is shared by two microphones. I2S carries a stereo pair per data line. TDM puts many slots on one shared line at a higher bit clock. This guide works out the clocks and pin counts and lists what to measure on your board.
If you are choosing a microphone interface for 2 to 8 mics, three things decide it: how many signal pins you can spend, what clock the bus needs, and what your SoC peripheral supports. This guide uses published numbers from the I2S specification, an Infineon MEMS mic datasheet and the ESP32-S3 reference manual. It does not contain a Duobay price or a measured result. It is an engineering summary of an interface choice, and it applies to any audio product category.
What do the sources say about each interface?
Each row below comes from a vendor or specification document. All were read on October 31, 2026. Re-check the document version before you design, because manuals are revised.
| Item | What the source says | Source |
|---|---|---|
| I2S wires | Three lines: serial clock (SCK), word select (WS) and serial data (SD). One data line carries two time-multiplexed channels, so one I2S data line is a stereo pair. The device that generates SCK and WS is the controller. | NXP I2S bus specification (UM11732), as of October 31, 2026 |
| PDM mic pins (Infineon IM69D130) | Five pins: DATA, VDD, CLOCK, SELECT, GND. SELECT sets left or right, so two mics share one DATA line and one CLK line in the stereo circuit. | Infineon IM69D130 datasheet, as of October 31, 2026 |
| PDM clock range (IM69D130) | The datasheet table lists a PDM clock frequency of 0.4 to 3.3 MHz. | Infineon IM69D130 datasheet, as of October 31, 2026 |
| PDM clock edge time (IM69D130) | Clock rise and fall time of 13 ns in the datasheet table. | Infineon IM69D130 datasheet, as of October 31, 2026 |
| TDM and PDM on one SoC (ESP32-S3) | The I2S controller receives up to 16 channels in TDM RX mode. A separate PDM RX mode uses only the WS (PDM clock) and DATA lines. PDM-to-PCM conversion in hardware is available on I2S0 only. | Espressif ESP32-S3 Technical Reference Manual, as of October 31, 2026 |
The Infineon rows come from a pin table row, a figure caption and the clock frequency row of the datasheet. Check the exact wording in the datasheet. We did not verify STM32, nRF54 or i.MX RT peripheral limits for this article. Take those from the official reference manual of your exact part.
How do the clocks work out?
PDM: clock equals decimation ratio times output rate
output_rate = pdm_clock / decimation_ratio
3.072 MHz / 64 = 48 kHzUnits: clock in hertz, ratio is a pure number, output rate in hertz. The 64x ratio is an example that makes the arithmetic clean. Your SoC filter sets the real ratio, so replace it with the value from your reference manual.
| Case | Calculation | Output rate | Note |
|---|---|---|---|
| PDM, 64x decimation, 3.072 MHz example clock | 3.072 MHz / 64 | 48 kHz | 3.072 MHz sits inside the 0.4 to 3.3 MHz range. The 64x ratio is the example ratio used in this article. Your SoC filter sets the real ratio. |
The clock range comes from the Infineon IM69D130 datasheet, as of October 31, 2026. The clock you pick sets the output rate your SoC can derive.
I2S and TDM: bit clock equals sample rate times slot width times slots
bit_clock = fs x slot_width x slots
48 kHz x 32 x 2 = 3.072 MHz
48 kHz x 32 x 8 = 12.288 MHz
48 kHz x 32 x 16 = 24.576 MHzUnits: fs in hertz, slot width in bits, slots as a count, bit clock in hertz. The 32-bit slot width and 48 kHz rate are example values to replace with your own.
| Bus | Calculation | Bit clock | Note |
|---|---|---|---|
| I2S, 2 slots of 32 bits | 48 kHz x 32 x 2 | 3.072 MHz | One stereo pair per data line. |
| TDM, 8 slots of 32 bits | 48 kHz x 32 x 8 | 12.288 MHz | Eight slots on one shared data line. |
| TDM, 16 slots of 32 bits | 48 kHz x 32 x 16 | 24.576 MHz | Sixteen is the ESP32-S3 TDM RX channel maximum cited above. |
The 16-slot case matches the 16-channel TDM RX maximum in the ESP32-S3 Technical Reference Manual (as of October 31, 2026). Whether a given SoC captures that many mics without drops is not stated in the sources, so measure it.
How many pins does each choice need?
The PDM count is one shared clock plus ceil(N/2) data lines, since two mics share a line through the SELECT pin. The I2S count is BCK and WS plus one data line per stereo pair. The TDM count assumes all mics fit on one shared line. Power and ground are not counted.
| Mics (N) | PDM | I2S | TDM, one shared line |
|---|---|---|---|
| 2 | 2 signal pins (CLK + 1 DATA) | 3 signal pins (BCK, WS, 1 DATA) | 3 signal pins (BCK, WS, 1 DATA) |
| 4 | 3 signal pins (CLK + 2 DATA) | 4 signal pins (BCK, WS, 2 DATA) | 3 signal pins (BCK, WS, 1 DATA) |
| 6 | 4 signal pins (CLK + 3 DATA) | 5 signal pins (BCK, WS, 3 DATA) | 3 signal pins (BCK, WS, 1 DATA) |
| 8 | 5 signal pins (CLK + 4 DATA) | 6 signal pins (BCK, WS, 4 DATA) | 3 signal pins (BCK, WS, 1 DATA) |
Pin counts are derived from the I2S bus specification and the IM69D130 datasheet, as of October 31, 2026.
What is the timing budget at 3.072 MHz?
period = 1 / 3.072 MHz = about 325 ns
half period = period / 2 = about 163 ns
rise/fall time (datasheet) = 13 nsThe datasheet rise and fall time is 13 ns, so the clock edges fill a small part of each half period. Skew between mics and ringing on the shared lines use the rest. The sources give no maximum trace length, skew or ringing figure for a real multi-mic board. We have no verified data for that either. The vendor did not publish it, so it has to be measured on your board.
What are the common traps?
These follow from the numbers above. They are engineering reasoning and do not describe a specific incident.
- Clock edges are a small slice of the period. At 3.072 MHz one clock period is about 325 ns and half a period is about 163 ns. The datasheet gives a 13 ns rise and fall time. Skew between the two mics on a shared DATA line, or between clock arrival at four mics, eats into that half period. These numbers let you set up the budget. They do not give a trace length, and we publish none.
- Sample-rate math can quietly drop the clock. At a fixed decimation ratio, a lower PDM clock gives a lower output rate. At 64x decimation, 3.072 MHz gives 48 kHz and half that clock gives 24 kHz. Pick the clock from the sample rate your audio chain needs.
- The controller owns the clock. In the I2S spec the device that generates SCK and WS is the controller. If your SoC is a peripheral on the bus and a codec or hub is the controller, clock routing and startup order change. Decide who drives the clock before you place connectors.
- Peripheral limits differ per SoC and per instance. On the ESP32-S3, hardware PDM-to-PCM conversion is on I2S0 only. A second I2S instance cannot be assumed to do the same job. Read the reference manual for your exact part and instance before you assign mics to pins.
- TDM raises the bus clock for the same sample rate. Eight 32-bit slots at 48 kHz need 12.288 MHz, four times the 3.072 MHz of a stereo I2S pair. A shared line saves pins and puts more edge-rate demand on one set of traces.
What should you measure on your own board?
The sources do not tell you how your layout, enclosure and SoC behave. We have not measured these for you. Set the pass line yourself for each row according to your product requirement, and record the basis for it.
| What to measure | How to probe or capture | Raw data to record |
|---|---|---|
| Clock and data edge quality at each mic | Probe CLK and DATA at the mic pins with a scope and a short ground spring. Repeat for each mic position, with the enclosure and cables in place. | Waveform captures at each pin, rise and fall times, visible ringing, probe type and bandwidth. |
| Skew between mics on a shared line | Capture CLK at the SoC and at the farthest mic on the same trigger. Measure the delay and how it changes with your layout. | Delay per mic position, trigger source, probe points, board revision. |
| Capture integrity with all mics running | Record from every mic for a long continuous run on the final firmware. Use a known test signal and check each channel for gaps, swapped channels and level offsets. | Raw captures per channel, buffer settings, DMA configuration, log of any dropped or swapped frames. |
| Left/right assignment | Drive each mic with a tone in turn, one at a time, and confirm which channel responds on every bus slot. | Mic position to slot mapping, SELECT pin state per mic, firmware channel map. |
| SNR and power at your chosen clock | Capture in a quiet room at each clock you are considering. Measure noise floor and current on the mic supply rail. | Clock frequency, decimation setting, noise floor in dB, rail current, measurement setup. |
| Behavior across SoC peripheral instances | Run the same capture on each I2S or PDM instance you might use. Confirm the PDM conversion path works on that instance. | Instance used, mode settings, pass or fail on conversion, reference manual page used. |
Write each pass line down before you run the test, with the reason you chose it.
What should you ask before you choose?
Take this list to your team and to any supplier who proposes a mic interface.
- How many mics do we need, and does the count fit in one stereo pair or does it need several data lines?
- Which device drives the clock, and does the SoC peripheral we chose support that role?
- Does the chosen peripheral instance offer PDM-to-PCM in hardware, or does the firmware decimate in software?
- Which output sample rate does our wake word, noise suppression and speech chain require, and which PDM clock and decimation ratio produce it?
- Have we measured the SNR and power change at a lower PDM clock on our chosen mic?
- How many signal pins can we spare on the SoC and on the flex or connector between boards?
- Where will each mic sit relative to the SoC, and how long are the clock and data runs?
- What does the reference manual of our exact MCU say about maximum TDM slots and PDM channels? Have we written the page number down?
- Does the product have a visible recording indicator and a documented consent flow?
- Which assumptions in our clock and pin plan are measured on our own board, and which are still guesses?
Products that capture audio should show a visible recording indicator and obtain consent. This article does not cover covert recording and nothing here supports it.
Questions about PDM, I2S and TDM
How many PDM mics can share one data line?
Two, based on the Infineon IM69D130 datasheet. Its SELECT pin sets left or right, and two mics share one DATA line and one CLK line in the stereo circuit. For more mics, add data lines: N mics need one clock plus ceil(N/2) data lines.
Is TDM always the better choice for many mics?
It saves pins, since one set of BCK, WS and DATA can carry many slots. It also raises the bit clock. Eight 32-bit slots at 48 kHz need 12.288 MHz. Whether that suits your board depends on your layout and your SoC, which you have to measure.
Can I pick a PDM clock lower than 3.072 MHz?
The IM69D130 datasheet table lists a PDM clock frequency of 0.4 to 3.3 MHz, and 3.072 MHz is inside that range. At a fixed decimation ratio the output rate drops with the clock. Check the datasheet for how SNR and power change at the clock you pick, and measure them on your board.
What is the maximum trace length for a PDM or TDM clock?
The datasheets and manuals cited here do not give one, and we have no measured limit to publish. The vendor did not publish it, so measure it on your own board with the table in this article.
Does this cover recording products?
This is an engineering comparison of interfaces. A product that records audio should have a visible indicator and a clear consent flow. See our audio and voice hardware page for how we scope these products.
If you are choosing a mic interface for a new device, tell us about your device. You can also read how our engineering gates handle this kind of decision, and see our guide to reading a MEMS mic datasheet.
Sources
All pages accessed October 31, 2026. Document versions change, so re-check them before you decide.
- NXP, I2S bus specification (UM11732): https://www.nxp.com/docs/en/user-manual/UM11732.pdf (accessed 2026-10-31)
- Infineon, IM69D130 datasheet: https://www.infineon.com/dgdl/Infineon-IM69D130-DataSheet-v01_00-EN.pdf (accessed 2026-10-31)
- Espressif, ESP32-S3 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf (accessed 2026-10-31)
Planning a voice or audio device? Tell us what it needs to do. A Duobay engineer replies within 1 business day. Send a project brief →