ESD Testing to IEC 61000-4-2 for Small Devices

Illustration

ESD testing to IEC 61000-4-2 fires a calibrated ESD gun at a working product, by contact on metal parts and by air discharge on insulating surfaces. Published levels run from 2 to 8 kV contact and 2 to 15 kV air. The product standard picks the level, and chip HBM ratings do not predict the result.

A finished device meets static every day. A user walks across a carpet, touches the charging contacts, and a few kilovolts land on your board. ESD testing shows what happens next: nothing, a reset, a hang, or a dead unit. This guide covers the system-level test, why chip ratings miss it, where a wearable gets zapped, and how TVS diodes and layout decide the result.

This is an engineering summary. IEC 61000-4-2 is a paid standard and we have not read its full text. Figures below come from the IEC catalog page and Texas Instruments application notes, as of November 2026. Confirm every level and procedure with your test lab.

What is ESD testing to IEC 61000-4-2?

IEC 61000-4-2 is the basic EMC publication for electrostatic discharge immunity. The current version is IEC 61000-4-2:2025, edition 3.0, published March 7, 2025. It replaced the 2008 second edition. The IEC page says it covers the ideal discharge current waveform, test levels, test equipment, setup, procedure, calibration and measurement uncertainty (IEC catalog page, as of November 2026).

Two limits on its scope matter. First, the standard leaves the choice of tests and severity levels to product committees, the IEC page says. Second, it does not cover ESD sensitivity during handling and packaging, and it is not meant for characterizing ESD protection circuits.

The 2025 edition added several annexes. The IEC page lists an informative annex for wearable devices (Annex J), an informative annex on choosing test points and the number of pulses for contact discharge (Annex E), and a normative annex on setups for particular kinds of equipment (Annex I). It also added a calibration requirement for air discharge tips (as of November 2026).

How the test runs

A lab uses a handheld ESD generator, often called an ESD gun. TI's summary of the standard lists a 150 pF network capacitance, a 330 Ω network resistance, at least 1 second between pulses, both polarities, at least 10 pulses, and a powered product (TI SLAA530B, revised July 2021, as of November 2026).

Direct discharges go to metal a user can reach in normal use. Indirect discharges go by contact to a horizontal or vertical coupling plane beside the product, which simulates a spark to a nearby object. TI says contact discharge is the preferred method, and that only insulated covers and connector pins in a plastic shell get air discharge.

Test levels

The levels below are from a TI article that reproduces the standard's level table. TI notes that a given level is not equally severe for the two methods, and that stress is usually stepped up above level 4 until the point of failure (TI SLYT492, 2012, as of November 2026). The article predates the 2025 edition, so confirm the table with your lab.

Why don't chip HBM and CDM ratings predict the result?

IC datasheets usually list ESD ratings such as Human Body Model (HBM) and Charged Device Model (CDM). These protect the chip while it is handled and assembled in a controlled factory. TI says device-level HBM, MM and CDM tests are intended only to ensure that ICs survive the manufacturing process, while IEC 61000-4-2 tests simulate end-user events (TI SLYT492, as of November 2026).

Rise times, device state, owner and failure rows: TI SLAA530B. Peak currents at 2 kV: TI SLYT492. Both as of November 2026.

The current gap is the key point. TI says a chip protected by 8 kV HBM, with a peak current of 5.33 A, can be destroyed by a 2 kV IEC strike with a peak of 7.5 A. The IEC test also repeats. TI's 2012 article says HBM uses a single positive and a single negative strike, while the IEC model uses ten of each, and a part can survive the first strike and fail on a later one (as of November 2026).

TI also notes that the Industry Council on ESD Target Levels concluded HBM 1 kV and CDM 250 V are enough for component-level ratings. For one MCU family, TI states plainly that it does not ensure system-level ratings such as IEC 61000-4-2 (TI SLAA530B, as of November 2026).

Where does a small wearable get zapped?

Start the protection plan with a list of every point a user can touch or come near. The rows below apply the direct, indirect, contact and air rules from TI SLAA530B to common wearable features. They are engineering reasoning. Your lab and product standard set the final points, and the 2025 edition has an annex on choosing them.

TI's enclosure guidance backs several rows. It advises a sufficient air gap between the PCB and points on the case such as vent holes, mounting holes and seams. It suggests switches with plastic shafts, or plastic knobs over metal shafts. It warns that LEDs and displays exposed through a plastic case form a direct discharge path into the system (TI SLAA530B, as of November 2026). In a wearable these choices belong in the enclosure design, before tooling. For the charging side of pogo pins and coils, see wireless charging for wearables.

How do you choose a TVS diode for ESD protection?

A transient voltage suppressor (TVS) is a diode, or an array of them, that stays open during normal use and shunts the ESD current to ground when the voltage exceeds its breakdown. TI names four parameters to check (TI SLYT492, as of November 2026).

• Breakdown voltage. The TVS must not break down below the line's maximum working voltage. Datasheets often state a working voltage at a given leakage. If not, TI suggests a minimum breakdown a couple of volts above the line's working voltage.
• Dynamic resistance. The resistance of the diode while it conducts. Lower is better. In 2012 TI called 1 Ω or less the industry standard value.
• Clamping voltage. The voltage your protected chip actually sees. TI warns that some TVSs survive an 8 kV contact discharge while the chip behind them is destroyed, because the clamp is too high.
• Capacitance. The TVS adds capacitance to the line in normal use. Count it in the bandwidth budget of fast lines such as USB.

Bidirectional or unidirectional, and other parts

A bidirectional TVS lets a signal swing above and below ground. TI says unidirectional parts suit high-speed lines because their steering diodes can be smaller, with less capacitance. TI SLAA530B adds that TVS diodes have lower capacitance and dynamic resistance than other suppressors. It says varistors typically have trigger voltages over 50 V and clamping over 100 V, and that polymer suppressors have 0.05 to 1 pF capacitance but lower endurance to repeated strikes. Small series resistors and capacitors help against secondary pulses, but TI says small SMD passives usually do not protect well against a direct 8 kV IEC pulse (as of November 2026). For a deeper guide to standoff, clamping voltage, capacitance and placement, see ESD protection design with TVS diodes.

How should TVS diodes be placed in the PCB layout?

A good TVS in the wrong place still fails. TI's layout guide shows why. In an 8 kV IEC event the current rises at about 30 A in 0.8 ns, or 4 × 10¹⁰ A/s. At that rate, just 0.25 nH of trace inductance adds about 10 V to the voltage the system sees (TI SLVA680A, revised April 2022, as of November 2026).

The guide's rules, in short:

• Place the TVS as near the connector or entry point as the design rules allow, and place the protected chip much farther away.
• Route the line straight from the entry point to the TVS pin. Avoid a stub between the line and the TVS.
• Ideally, put no via between the entry point and the TVS.
• Make the TVS path to ground as short as possible. TI calls this inductance perhaps the largest parasitic acting on the voltage of the protected line.
• Keep unprotected traces away from the stretch between the entry point and the TVS, on every layer a via crosses.
• Use curved corners on that stretch, or 45° at most.

On a small board these rules compete for space. For layout rules on small battery boards, see PCB layout for small battery-powered devices.

How are ESD test results judged, and what should firmware do?

The test does not end at whether the unit survives. TI lists the IEC classification of results (TI SLAA530B, as of November 2026):

• Normal performance within the limits the manufacturer specifies.
• Temporary loss of function or performance that ends when the disturbance ends, with recovery and no operator action.
• Temporary loss of function or performance that needs operator action to recover.
• Loss of function that is not recoverable, from damage to hardware or software, or lost data.

TI says most system-level ESD failures are soft failures: the system upsets without physical damage. So firmware decides much of the result. TI recommends a watchdog that the software never stops once started, short timeouts inside functions, oversampling of critical inputs, parity and framing checks on incoming data, and retransmission when an acknowledgment does not arrive. On the circuit side it advises terminating unused pins and keeping reset and interrupt lines off long traces (as of November 2026).

Agree on the acceptable class before testing. A recording wearable that reboots and drops a recording may be in a different class from one that recovers mid-file. TI says acceptance criteria are specific to each system, and it notes that ESD testing is too often left as an afterthought.

When to test

TI advises ESD testing throughout design and development to find weak spots. A practical rhythm is a quick in-house gun check on early boards, again on units in production-intent enclosures, then the formal lab run. For what each build stage should deliver, see EVT, DVT and PVT. ESD immunity is one part of EMC. For emissions and the other immunity tests, read the next article in this series, EMC testing for electronics.

What should you ask your hardware team?

Bring this list to the first design review, before layout and enclosure are frozen.

• Which product standard sets our ESD level, and which level and performance criterion does it call for at each point?
• Which edition of IEC 61000-4-2 will the lab test to, and how does it pick test points and pulse counts?
• Have we listed every point a user can touch, including charging contacts, seams and ports?
• For each exposed signal, which TVS is fitted, and what are its working voltage, clamping voltage, dynamic resistance and capacitance?
• Is each TVS at the connector, with no stub and no via between the entry point and the diode?
• How short is the path from each TVS to ground, and which ground does it use?
• What does the firmware do after an upset? Is there a watchdog, and does the device recover without a user?
• When do we run our own ESD gun checks before the lab: on EVT boards, DVT units, or both?

Write the ESD level, the entry-point list and the acceptable performance class into the product requirements early. See what Gate 0 Feasibility covers.

If you want ESD protection planned into your device from the first board, tell us about your device.

Sources. All pages accessed November 6, 2026. Standards and application notes are revised, so confirm current values before you decide.

• IEC, IEC 61000-4-2:2025, Electromagnetic compatibility (EMC), Part 4-2: Electrostatic discharge immunity test, edition 3.0, catalog page (link)
• Texas Instruments, Design considerations for system-level ESD circuit protection, Analog Applications Journal 4Q 2012, SLYT492 (link)
• Texas Instruments, MSP430 System-Level ESD Considerations, SLAA530B (March 2012, revised July 2021) (link)
• Texas Instruments, ESD Protection Layout Guide, SLVA680A (February 2015, revised April 2022) (link)