IllustrationGood PCB layout in a small battery device starts with the outline, battery and antenna, then the power path and main chip. Keep a solid ground plane under every RF, clock and high-speed trace, put decoupling capacitors at their pins, keep battery current paths short and wide, and reserve test points before routing.
A small battery device leaves little room for a second try. The antenna sits millimeters from the battery, the charger shares ground with the radio, and the enclosure fixes every connector. This guide covers the layout rules that matter most there, in the order a layout engineer meets them. The numbers come from chip vendor guides and manufacturer design guides linked below, as of November 2026. Follow the guide for the chip you actually use.
What does PCB layout decide in a small battery device?
The schematic says what connects to what. The layout decides how well those connections work. In a small device it sets four outcomes that no later change to the schematic can fix.
- Radio range. Antenna position, ground under the RF trace and clearance in the housing all change how much power reaches the air.
- Noise and emissions. Current always returns to its source. TI's EMI note treats every loop as an antenna whose radiation grows with its area, up to a quarter wavelength, as of November 2026 (TI SZZA009). A broken return path makes the loop bigger.
- Battery behavior. Long, thin power traces add voltage drop and noise. A fuel gauge with poor sense connections reads the wrong current.
- Build and test cost. Missing test points or tight edge clearances slow the factory test, or block it, until the board changes.
Each of these is cheap to get right before routing and costly to fix after the first boards arrive. For where layout sits in the full sequence from requirements to bring-up, see the PCB design process.
In what order should you place parts on the board?
Place the parts with no freedom first. This order for a small wireless device is engineering practice drawn from the vendor guides below. Your enclosure may change it.
| Step | What you place | Why now |
|---|---|---|
| 1. Outline, enclosure, battery | Board shape, battery pocket, mounting points, tallest parts. | The housing and the cell set most of the board shape. |
| 2. Antenna or RF module | Antenna edge, keep-out, RF feed. | Antenna rules move other parts, so they come early. |
| 3. User-facing parts | Charging contacts, buttons, mic holes, sensor windows. | The enclosure fixes their positions. |
| 4. Power path | Charger, protection, sense resistor, regulators. | Short, wide power loops need room near the battery. |
| 5. Main chip and crystal | SoC or MCU, crystal, memory, decoupling capacitors. | Vendor guides fix crystal spacing and decoupling position. |
| 6. Test and programming access | Test pads, debug header, fiducials. | Pad rules depend on the fixture. Reserve space now. |
| 7. Routing | RF first, then clocks and fast pairs, then power, then the rest. | Impedance-controlled lines need a whole plane under them. |
Sierra Circuits, a board manufacturer, says the stack-up must be designed before layout starts and that footprints must exist before you start the design (Sierra Circuits layout guide, as of November 2026). In a small device, also check every placement against the enclosure model. A capacitor under a screw boss is a layout error even when every electrical rule passes. Charging contacts and buttons from step 3 are also where static enters the board. ESD protection design with TVS diodes covers the parts placed beside them.
How do ground planes and return paths work on a small board?
Signal current flows out on its trace and back through ground. At high frequency the return follows the ground directly under the trace. If that ground is whole, the loop stays small. If a slot or split cuts it, the return goes around and the loop grows.
What the vendor notes say
- TI's EMI note calls signal return paths the most difficult design problem in PCB layout. A four-layer board's ground plane gives every trace a return path underneath (TI SZZA009, November 1999, read as of November 2026).
- The same note says holes and cutouts in a plane increase loop area, and a row of holes is much better than a long slot. When the plane is split, signals tied to the processor should stay entirely over the digital ground.
- TI's wireless MCU guide shows a break in the layer 2 ground making a longer return path, and warns of reduced RF performance and higher spurious emissions (TI SWRA640H, revised May 2024, section 4.7, as of November 2026).
Two layers or four?
The 1999 TI note says a two-layer board can achieve 95% of the effectiveness of a four-layer board if you route ground under power, grid power and ground, and run returns under processor I/O traces (TI SZZA009, section 2.1.2, as of November 2026). That note discusses microcontroller boards. For a radio chip, read the chip vendor first. Espressif recommends a four-layer stack for the ESP32-S3, with layer 2 kept as ground and no signal traces, and gives separate two-layer rules (Espressif guide, as of November 2026).
What PCB layout guidelines do chip vendors publish for RF and antennas?
Radio chip vendors publish layout rules for their own parts. The table collects rules from two of them, as of November 2026. Values for one chip do not carry over to another.
| Rule | What the guide says | Source |
|---|---|---|
| Layer stack | Four-layer board recommended. Layer 2 is ground with no signal traces. | Espressif ESP32-S3 guide, as of November 2026 |
| Ground vias under the chip | At least nine vias from the chip's bottom ground pad to the ground plane. | Espressif ESP32-S3 guide, as of November 2026 |
| Crystal position | At least 2.0 mm from the chip's clock pin. No vias on the clock traces. | Espressif ESP32-S3 guide, as of November 2026 |
| RF trace | 50 Ω, no vias, bends at 135° or as arcs, whole ground plane on the next layer. | Espressif ESP32-S3 guide, as of November 2026 |
| Module antenna | Antenna outside the base board, or feed point near the board edge. Cut the base board beside and below the antenna. | Espressif ESP32-S3 guide, as of November 2026 |
| Housing clearance | At least 15 mm around the PCB antenna in all directions. | Espressif ESP32-S3 guide, as of November 2026 |
| Ground under RF parts | Solid ground under all RF components, from the antenna back to the chip pad vias. No traces under the RF path. | TI SWRA640H, 4.2, as of November 2026 |
| Stack-up | Top-to-ground distance should match the reference design, or the filter balun may need a redesign. | TI SWRA640H, 4.1, as of November 2026 |
Two of these rules often collide with a small enclosure. A wearable or tag rarely has 15 mm free around the antenna on every side, so decide early what gives: board shape, battery position or antenna type. The stack-up is the second. Ask your fab for its stack-up before layout and compare it with the reference design. Our guide to PCB layers and thickness covers how many layers a small device needs. For trackers, our GNSS antenna placement guide covers the satellite antenna. For antenna types, matching networks and tuning inside the housing, see PCB antenna design for small devices.
Keep slow, noisy lines away from the antenna too. Espressif asks that UART traces, vias, test points and header pins sit as far from the antenna as possible (Espressif guide, as of November 2026).
Where do decoupling capacitors and battery current paths go?
Decoupling capacitors
A decoupling capacitor supplies the fast current a chip draws on each clock edge. It works only if the loop from capacitor to pin to ground is short. TI's wireless MCU guide asks you to (TI SWRA640H, section 4.5, as of November 2026):
- put the capacitor on the same layer as the chip,
- route power into the capacitor first, then into the pin,
- give each capacitor its own via to ground,
- place it close to its pin, with a short, direct ground return.
Espressif asks for a 10 µF capacitor before the power trace enters the ESP32-S3, and a 10 µF capacitor on each of its two RF-related supply pins, and allows one 10 µF capacitor to serve both when the power entrance sits next to those pins (Espressif guide, as of November 2026). For the crystal, TI asks for a short, symmetrical loop through both load capacitors, with their grounds close together (TI SWRA640H, section 4.6, as of November 2026).
High-current battery paths
A wireless device draws current peaks when the radio transmits. Every trace and via between the cell and the regulator adds resistance and inductance.
- TI's switching-regulator note asks for short, direct, thick power traces, at an absolute minimum of 15 mils (0.381 mm) per ampere on a standard board, and one standard via per 200 mA between planes (TI AN-1149, revised April 2013, as of November 2026).
- It puts the input capacitor as close to the VIN pin as possible, keeps the inductor, output capacitors and diode together, and runs the feedback trace away from the inductor.
- It also asks that the switching current loops curl in the same direction in both switch states, to reduce radiated EMI.
- TI's bq27441-G1 fuel gauge datasheet asks for SRP and SRN to be Kelvin connected to the sense resistor, and BAT Kelvin connected to the pack positive terminal (TI SLUSBH1C, section 12.1, as of November 2026).
Treat 15 mils per ampere as a floor for regulator traces. Copper weight, temperature rise and length change the real answer, so confirm widths with your fab.
How do you plan test points and DFM before routing?
Test points need space, and a small board runs out of space first. Decide how the boards will be tested, then reserve pads to match. The two guides below disagree, which shows that the right numbers depend on the fixture your test house uses. Both as of November 2026.
| Item | Sierra Circuits DFT guide | FixturFab DFT guide |
|---|---|---|
| Pad diameter (fixture test) | 0.7 mm recommended, 0.6 mm minimum, boards up to 300 mm | Over 1.0 mm preferred, 0.8 mm minimum |
| Pad spacing (center to center) | 2.1 mm for 100 mil nails, 1.7 mm for 75 mil nails | Over 1.9 mm preferred, 1.27 mm minimum |
| Distance to board edge | 0.9 mm, and 3 mm from the locating edge | 5 mm preferred, 3.175 mm minimum |
| Distance to parts | 0.7 mm for parts under 2 mm tall | Over 1.5 mm preferred, 1.0 mm minimum, more for tall parts |
| Solder mask | None on the test point | Via test points must be untented |
| Board side | All nets from one side, with limited exceptions | All test points on one side |
Sierra Circuits also asks for at least one probe point per net and three fiducials per board (Sierra Circuits DFT guide, as of November 2026). Its layout guide gives pads at least 1.8 times the hole diameter, or at least 0.5 mm larger, and a 10:1 aspect ratio for through-hole vias (Sierra Circuits layout guide, as of November 2026). Your fab's own capability sheet overrides any general figure. Get a DFM review before you order boards, and keep the result with the layout files.
A sealed device also needs a plan for testing after assembly. Decide how firmware is loaded and how the battery rail is measured once the housing is closed. One option is a set of pogo-pin pads a fixture can reach through the charging area. The choice changes the layout, so make it before routing. For which test methods need those pads, and how to plan factory programming and test firmware, see in-circuit test vs functional test.
What should you ask your hardware team before layout review?
Take these questions to the review.
- Which vendor layout guide and reference design does this board follow, and which revision?
- Where does the board differ from the reference stack-up or RF layout, and who checked the effect?
- Which plane sits under each RF trace, clock and USB pair, and is it whole?
- What is the antenna clearance to the battery, screws and any metal in the housing?
- What is the peak battery current, and what trace widths and via counts carry it?
- Is the fuel gauge sense resistor Kelvin connected as its datasheet asks?
- Do the test pads meet the fixture rules of the house that will test the boards?
- What did the fab's DFM check flag, and which items were waived?
If the answers are written down, the review moves fast. If not, the board is not ready to order. The engineering page shows how the electronics work is organized, and the prototype gates show where the first custom board fits.
Is a two-layer board enough for a small Bluetooth or Wi-Fi device?
Sometimes. Check the chip vendor first. Espressif recommends four layers for the ESP32-S3 and asks for a complete ground plane under the chip, RF and crystal on a two-layer board, as of November 2026 (Espressif guide). The answer depends on your radio chip, board area and how much routing must pass under the RF section.
Can I move the antenna away from where the module guide shows it?
You can, but the vendor results then no longer apply as written. TI says moving the balun, match and filter parts may require retuning, which needs RF skills and equipment (TI SWRA640H, as of November 2026). Plan to measure the antenna match in the real enclosure.
Which standard sets trace width for battery current?
IPC-2152, Standard for Determining Current Carrying Capacity in Printed Board Design, covers this, as of November 2026 (IPC design standards). We quote no values from it here. Ask your fab which copper weight and temperature rise they assume.
How can Duobay help with PCB layout for my device?
Duobay's Shenzhen team does the electrical, firmware, mechanical and test work for a custom device, and layout is part of that full device project. We do not take board-only layout jobs. All source files, including schematics and layout source, are assigned to you at each paid gate. We do not publish prices. Tell us about your device and we will explain how a project would run.
If you are planning a small battery device and want the layout done as part of the full device project, tell us about your device.
Sources
All pages accessed November 5, 2026. Vendor guidance applies to the parts each source describes. Re-read the current revision for your own chip before you rely on any figure.
- Espressif, ESP32-S3 PCB layout design (ESP Hardware Design Guidelines): https://docs.espressif.com/projects/esp-hardware-design-guidelines/en/latest/esp32s3/pcb-layout-design.html (accessed 2026-11-05)
- Texas Instruments, SWRA640H, CC13xx/CC26xx Hardware Configuration and PCB Design Considerations, revised May 2024: https://www.ti.com/lit/an/swra640/swra640.pdf (accessed 2026-11-05)
- Texas Instruments, SZZA009, PCB Design Guidelines for Reduced EMI, November 1999: https://www.ti.com/lit/an/szza009/szza009.pdf (accessed 2026-11-05)
- Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies, SNVA021C, revised April 2013: https://www.ti.com/lit/an/snva021c/snva021c.pdf (accessed 2026-11-05)
- Texas Instruments, bq27441-G1 datasheet, SLUSBH1C, revised December 2014: https://www.ti.com/lit/ds/symlink/bq27441-g1.pdf (accessed 2026-11-05)
- Sierra Circuits, Design for Testing Guidelines for PCB: https://www.protoexpress.com/blog/design-for-testing-guidelines-pcb-manufacturing (accessed 2026-11-05)
- Sierra Circuits, PCB Layout Design: https://www.protoexpress.com/kb/pcb-design-layout/ (accessed 2026-11-05)
- FixturFab, SMD Test Points and Design-for-Test Guidelines: https://fixturfab.com/resources/how-to-test/design-for-test (accessed 2026-11-05)
- IPC, IPC Design Standards (IPC-2152 title): https://www.ipc.org/ipc-design-standards (accessed 2026-11-05)
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