Concept renderA PCB via is a plated hole that joins copper layers. Through-hole vias span the whole board and need the fewest steps. Blind vias start at an outer layer, buried vias stay between inner layers, and microvias are laser-drilled holes under 150 µm. Each type past through-hole adds process steps, so let your densest package set the via type.
Via choice looks like a layout detail. It decides how many lamination cycles the board needs, which fabs can build it, and how the parts solder at assembly. This guide compares the via types, the aspect ratio limits fabs publish, and how each choice affects the build. Every figure is linked to a fab guide, a trade column or a chip vendor note.
This is an engineering summary. Fab limits change and differ between shops, so confirm every number with the fab that will build your board. We quote no threshold from paywalled IPC standards.
What is a PCB via, and which types are there?
A via is a drilled hole with copper plated on its wall. It carries a signal, power or heat from one copper layer to another. Types differ in which layers the hole spans and how it is made. Each new drill method or span adds steps at the fab.
| Via type | Connects | How it is made | Where it fits |
|---|---|---|---|
| Through-hole via | Top layer to bottom layer. | One mechanical drill through the full board, then copper plating. | The default on most boards. |
| Blind via | An outer layer to an inner layer. | Controlled-depth or laser drilling, from its own drill file. | Frees routing space on layers it does not reach. |
| Buried via | One inner layer to another inner layer. | Drilled in inner layers that are laminated before the full stackup. | Frees both outer layers for parts and routing. |
| Microvia | Usually one layer to the next adjacent layer. | Laser drilled, under 150 µm in diameter. | Fine-pitch BGA and chip-scale fanout on HDI boards. |
| Via-in-pad | From a surface-mount pad down into the board. | Drilled in the pad, then filled and covered with copper plating. | BGA pitches of 0.5 mm or less, per Sierra Circuits as of November 2026. |
| Tented, plugged or filled via | Any of the spans above. | Solder mask over the hole, or a plug or fill material in the barrel. | Protects the barrel and controls solder at assembly. |
How do blind vias and buried vias change the build?
Both types end inside the board. AdvancedPCB says they increase cost because they need multiple lamination cycles, precision drilling and extra inspection (as of November 2026).
Blind vias
A blind via starts on the top or bottom layer and stops on an inner layer. AdvancedPCB says the fab uses a drill file that sets each via's start and stop layer, and it must control drill depth tightly. Because the hole does not run the full board, it leaves less unused stub, which helps signal integrity at higher frequencies (as of November 2026).
Buried vias
A buried via connects inner layers only. Those layers are laminated together before the full stackup, and each buried set usually gets its own drill file. AdvancedPCB says fabs often limit buried vias to a depth-to-diameter ratio of around 10 to 12:1 or less (as of November 2026).
Ask the fab how many lamination cycles your stackup needs before you commit to it.
What counts as a microvia, and how far can you stack them?
Sierra Circuits cites IPC-T-50M for the definition it uses: a laser-drilled hole under 150 µm in diameter, with a target length of no more than 0.25 mm from capture land to target land (as of November 2026). AdvancedPCB says microvias usually connect one layer to the next adjacent layer.
Microvias can sit on top of each other (stacked) or step sideways (staggered). Sierra Circuits advises staggered. It says staggered microvias survive more thermal cycles than stacked ones, and that stacked microvias increase cost. It suggests stacking only where routing density is extremely high, such as under fine-pitch BGAs (as of November 2026).
Sierra Circuits also says IPC-2226 defines HDI build-up types I, II and III, and that IPC-TM-650 2.6.27 tests microvia reliability on D-coupons, failing a rise in resistance above 5% (as of November 2026). We have not read either standard, so treat that as the fab's summary. For build-up types and microvia reliability on small devices, see HDI PCB design for wearables.
What aspect ratio limits apply to each via?
Aspect ratio is board or dielectric thickness divided by hole diameter. Deep, narrow holes are hard to plate. AdvancedPCB says reduced solution exchange inside a deep hole can leave thinner copper in the center of the barrel, and these thin areas become potential failure points during thermal cycling (as of November 2026).
| Via | Published limit | Source, as of November 2026 |
|---|---|---|
| Through-hole, standard | 6:1 to 8:1 | AdvancedPCB drill aspect ratio guide |
| Through-hole, advanced | Up to 10:1. Sierra Circuits calls 10:1 the ideal ratio for a through-hole via. | AdvancedPCB guide and Sierra Circuits via design guide |
| Through-hole, high-control | Up to 12:1, with engineering review | AdvancedPCB drill aspect ratio guide |
| Buried via (mechanical) | Fabs often limit depth to diameter to around 10 to 12:1 or less | AdvancedPCB blind and buried via guide |
| Laser microvia | 0.75:1 to 1:1. Sierra Circuits calls 0.75:1 ideal and advises staying at or below it. | AdvancedPCB guide, Sierra Circuits via and microvia guides |
| Stacked microvias | About 1:1 per microvia layer | AdvancedPCB drill aspect ratio guide |
Two details trip teams up. First, the shops divide by different things. AdvancedPCB divides board thickness by the finished hole diameter. Sierra Circuits divides by the drilled hole diameter. A plated hole finishes smaller than its drill, so the same hole gives two ratios. Second, a microvia ratio uses the dielectric thickness between adjacent layers in place of the board thickness. Both points are from the two shops' guides as of November 2026.
A worked example from AdvancedPCB: a 0.062 in (1.57 mm) board with a 0.012 in (0.30 mm) finished hole has a ratio of about 5.2:1. Before a design goes past standard through-hole limits, AdvancedPCB suggests a thinner board, blind and buried vias, or HDI structures (as of November 2026).
When do you need via-in-pad, tented, plugged or filled vias?
IPC-4761 is the design guide for protecting via structures. A design-tool vendor summary of it lists seven types and marks the single-sided versions of Types I to IV as not recommended. The notes in the table come from an I-Connect007 column by a field application engineer at a PCB supplier, so read them as one shop's advice.
| IPC-4761 type | Name | Notes from the column |
|---|---|---|
| Type I | Tented via | Mask bridges the hole. IPC does not recommend the single-sided version. |
| Type II | Tented and covered via | Single-sided version not recommended. The author advises against it inside a BGA footprint. |
| Type III | Plugged via | IPC does not recommend the single-sided version. |
| Type IV | Plugged and covered via | Same note on the single-sided version. |
| Type V | Filled via | No specific note. |
| Type VI | Filled and covered via | The author recommends filling to at least 70%. |
| Type VII | Filled and capped via | Needs highly specialized equipment to draw the resin into the via. |
Sources: Altium IPC-4761 summary and I-Connect007, 7 Options for Via Treatment (2020), both as of November 2026.
Via-in-pad
Sierra Circuits says via-in-pad holes need to be filled and covered with copper plating. Its via design guide says they must be filled unless they sit in thermal pads. Filling stops solder wicking into the hole and trapped gas during reflow. Vias under a BGA should be filled and planarized, or the joints may be compromised. List filled vias in a separate drill file and state the fill type in the fab notes. Conductive fill costs more and suits high current (as of November 2026).
Thermal vias under exposed pads
TI's note SLUA271C covers exposed pads on QFN and SON parts. TI says the thermal data in its datasheets assumes a four-layer board with vias, per JESD51-7. Not every application needs vias. For thermally hard cases TI suggests a via pitch of about 1.0 mm and a 0.3 mm drill as a starting point, and says a smaller via risks less solder loss. Plugged vias remove that risk. Tenting from the back can trap air and raise voiding, and top-side tenting needs a mask opening 0.1 mm larger than the hole (TI SLUA271C, as of November 2026). The datasheet land pattern for your exact part comes first.
How does via choice change layer count, cost and assembly?
Start from the densest package on the board, then work outward. That part usually decides the via type, and the via type decides the stackup. The rows are engineering reasoning from the sources above, and none describes a specific project.
| Situation | Via approach | What it adds |
|---|---|---|
| Every package has a pitch you can fan out with a via between pads | Through-hole vias, tented or plugged as your fab advises | Nothing beyond the standard process. |
| A QFN or SON with an exposed pad that must shed heat | Thermal vias in the pad, plugged or tented, following the land pattern in the part datasheet | Plugging adds a step. Tenting is cheaper but can trap air or chemistry if done from the wrong side. |
| A BGA or chip-scale package at 0.5 mm pitch or less | Often via-in-pad, filled and capped, sometimes as laser microvias. Some 0.5 mm parts can still escape with vias between pads on more layers (TI SPRABB3). | An extra drill file for filled vias, fill and planarize steps, and an HDI-capable fab. |
| The board is thick and the holes are small, so the ratio passes the fab limit | A thinner board, a larger drill, or blind and buried vias | Thinner boards change stiffness and impedance. Blind and buried vias add lamination cycles. |
| Dense routing on several layers under one fine-pitch part | Staggered microvias, with stacked ones only where space forces them | Sierra Circuits says stacked microvias increase cost. |
Denser vias can also save board area or layers. AdvancedPCB says blind and buried vias free routing space and help shrink the board, and Sierra Circuits says microvias enable higher routing density by reducing the layer count (both as of November 2026). Quote both stackups to see whether the savings offset the extra lamination. On a small device, a package choice made early, such as a chip-scale part instead of a QFN, can commit you to HDI before anyone draws the board. See MCU or Linux SoC for a wearable.
Assembly feels it too. Open vias in pads pull solder from joints, and back-side tenting can raise voiding. Write the via treatment into the fab drawing so the board house and the assembler work from the same instructions.
What should you ask your hardware team?
Bring this list to the stackup review before layout starts, and write down which fab confirmed each answer.
- Which part forces the via type? Name the part number and pitch.
- What aspect ratio does the chosen fab allow, and does it divide by the drilled or the finished hole size?
- Does the stackup need sequential lamination, and how many cycles?
- Which IPC-4761 type is called out for each via class, and is it written in the fab notes?
- Are via-in-pad holes listed in their own drill file, and is the fill conductive or non-conductive?
- Are any microvias stacked? If so, why can they not be staggered?
- For each exposed-pad part, does the layout follow the datasheet land pattern and say plug, tent or open?
Via and stackup decisions sit inside the electronics work at the PCB prototype stage. For how the electronics work is organized, see engineering.
Questions about PCB vias
What is the difference between a blind via and a buried via?
A blind via runs from an outer layer to an inner one. A buried via runs only between inner layers. Each usually gets its own drill file (AdvancedPCB, as of November 2026).
Is a microvia the same as a blind via?
Blind describes the span. Microvia describes size and drilling: laser drilled and under 150 µm, in the IPC-T-50M summary from Sierra Circuits (as of November 2026). A laser microvia from an outer layer is also a blind via.
Should vias be tented, plugged or filled?
Sierra Circuits says vias in a pad must be filled and covered with copper plating unless they sit in thermal pads (source, as of November 2026). Vias under exposed pads can be plugged or tented, and TI found top-side tenting less likely to cause random voids (TI SLUA271C, as of November 2026). Ask your fab which IPC-4761 types it builds.
Do blind and buried vias always cost more?
AdvancedPCB says they increase cost because they need extra steps: multiple lamination cycles, precision drilling and more inspection (source, as of November 2026). They also free routing space, so compare quotes for both stackups.
How can Duobay help with via and stackup choices?
Duobay develops custom devices with a Shenzhen engineering team, and the stackup and via plan are part of the electronics work. Source files are assigned to you at every paid gate. We do not publish prices, and initial calls are free. Tell us about your device.
If you want a stackup and via plan checked against the packages your device needs, tell us about your device.
Sources. All pages accessed November 5, 2026. Fab limits and standards are revised, so confirm current values before you decide.
- AdvancedPCB, How PCB Drill Aspect Ratio Impacts Manufacturing (posted June 16, 2026) (link)
- AdvancedPCB, blind and buried vias guide, Key Manufacturing Insights (link)
- Sierra Circuits, PCB via design guide (link)
- Sierra Circuits, Via-in-pad (link)
- Sierra Circuits, How to Design Reliable Microvias in Your PCBs (November 24, 2025) (link)
- Altium, IPC-4761 via protection types summary (link)
- I-Connect007, Fresh PCB Concepts: 7 Options for Via Treatment (June 18, 2020) (link)
- Texas Instruments, QFN and SON PCB Attachment, SLUA271C (revised December 2023) (link)
- Texas Instruments, PCB Design Guidelines for 0.5mm Package-on-Package Applications Processor, SPRABB3 (June 2010) (link)
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