IllustrationSMT PCB assembly prints solder paste through a stencil onto the pads, places surface-mount parts by machine, melts the paste in a reflow oven, then inspects joints with AOI and, for hidden joints under BGA and QFN parts, X-ray. The assembler also needs a clean BOM, a placement file, paste layers and fiducials.
Most SMT guides list the machine steps and stop. A product team also needs to know what to hand the assembler, which rules change on a small first batch, and which defects show up on prototype boards. This guide covers all three, with numbers from a chip vendor app note, a module datasheet and two PCB fabricators' design guides, as of November 2026. It contains no Duobay price and no test result of ours.
What is SMT PCB assembly, and how does surface mount technology differ from through-hole?
Surface mount technology (SMT) solders parts onto pads on the surface of the board. Through-hole parts have leads that pass through drilled holes and are soldered on the far side. SMT parts are smaller, and machines can place them on both sides of the board, which suits wearables, trackers and voice devices.
An SMT PCB is a bare board designed for this process, and the assembled board is often called a PCBA. Assembly quality depends on layout decisions made long before the line: pad and paste shapes, via treatment, fiducials, part spacing and which side each part sits on. For where those decisions fall in the board design steps, see the PCB design process.
What are the SMT assembly steps, from stencil to inspection?
A typical line runs six steps. Double-sided boards go through the line twice, once per side. Figures in the table are as of November 2026.
| Step | What happens | Vendor guidance | Source |
|---|---|---|---|
| 1. Paste print | A squeegee pushes solder paste through openings in a thin metal stencil onto the pads. | Foils of 0.100 to 0.150 mm, with 0.125 mm typical for 0.5 mm pitch parts. | TI SLUA271C |
| 2. Paste inspection | Deposits are checked for position and volume before any part is placed. | A repeatable deposit is the most important factor for reflow yield. | TI SLUA271C |
| 3. Pick and place | Machines take parts from feeders and set them on the wet paste, using fiducials to find the board. | Start QFN placement force at 1.5 N. Parts more than 50% off the pad center must be removed before reflow. | TI SLUA271C |
| 4. Reflow | An oven melts the paste, forms the joints, then cools the board. | Check the profile on every new board, at several board locations, with thermocouples at real joints. Ramp at 4 °C per second or less. | TI SLUA271C |
| 5. AOI | Cameras compare each board with a reference to flag missing, shifted or reversed parts. | AdvancedPCB lists in-line AOI, plus 2D, 2.5D and 3D X-ray for hidden solder joints. | AdvancedPCB |
| 6. X-ray | Transmission X-ray shows hidden joints, such as BGA balls and QFN exposed pads. | Detects bridging, shorts, opens and voids. Usually used to set up and monitor the process, and 100% inspection is uncommon. | TI SLUA271C |
Stencil and paste
The stencil sets how much solder each joint gets. The area ratio is the opening area divided by the area of the opening walls. The aspect ratio is the opening width divided by the foil thickness. TI states that stencil makers require an aspect ratio above 1.5, and that openings with an area ratio below 0.66 need a nickel-formed stencil instead of a laser-cut one (TI SLUA271C, as of November 2026). AdvancedPCB says there is no single correct thickness for every board, since fine-pitch parts and large parts pull in opposite directions (AdvancedPCB stencil guide, as of November 2026).
Reflow profile
The profile has to respect the most heat-sensitive part on the board. TI's example lead-free profile for QFN parts peaks between 230 °C and 260 °C, and TI qualifies those parts for three reflows. The ESP32-S3-WROOM-1 module datasheet gives a peak of 235 to 250 °C with SAC305 solder and says to solder the module in a single reflow (Espressif datasheet v1.8, as of November 2026). On a board with both, the module sets the limits and decides which side is built first.
AOI and X-ray
AOI checks what a camera can see from above. It cannot see under a BGA or a QFN exposed pad, so those joints need X-ray. On a first build the process is still being set up, so ask for X-ray results on every hidden-joint part.
Which assembly files drive the SMT process itself?
The full file package for an assembled board (Gerber or ODB++, BOM, assembly drawing and the rest) is covered in PCB vs PCBA: which files a PCBA order needs. The rows below are the files that set the stencil, the placement program, the panel and the oven. The placement errors come from a Sierra Circuits list of design mistakes (Sierra Circuits, as of November 2026). The paste and module rows draw on the TI app note and the Espressif datasheet cited below.
| File | What it contains | Common error to check |
|---|---|---|
| Paste layers | Top and bottom paste layers, which set the stencil openings. | Openings copied 1:1 onto large exposed pads. |
| Placement file (centroid, XY or CPL) | Designator, X and Y position, rotation and side for each part. | Wrong units (mm against inches) and rotations that do not match the footprint. |
| Panel drawing | Array layout, rails, tooling holes, panel fiducials, V-score or tab locations. | No drawing approved by the assembler before the boards are ordered. |
| Fab and assembly notes | Via treatment, surface finish, parts with reflow or cleaning limits. | A module that allows one reflow, or must not see ultrasonic cleaning, with no note saying so. |
Keep these files under version control with the schematic and layout. They belong in the same handover as the firmware and SBOM. See what goes in a source-file handover.
How do you prepare a small-batch SMT build: panels, fiducials and part packaging?
A small device board is often too small for a machine to hold. The fab ships it in a panel with rails and fiducials, and the boards are broken out after assembly. The values below are starting points from two PCB fabricators, as of November 2026. They do not always agree, so confirm final values with the shop that builds your boards.
| Item | Starting rule | Source |
|---|---|---|
| Global fiducials | Three, not in a line, near board or panel corners. Pad 1.0 to 2.0 mm, mask clearance 2.0 to 4.0 mm. | AdvancedPCB |
| Local fiducials | Two per critical part, diagonally outside the body, when pitch is 0.5 mm or finer. Pad 0.5 to 1.0 mm, clearance 1.0 to 2.0 mm. | AdvancedPCB |
| Fiducials, second source | Diameter 1 to 3 mm, at least 3 mm from the board edge, no solder mask on the mark. | Sierra Circuits |
| Spacing between boards | One Sierra Circuits page gives 0.1 in of routing space; its DFA checklist gives a 0.2 in gap. Ask your fab. | Sierra Circuits |
| Keep-out from tabs | Traces and SMD parts at least 118 mil from tabs. Use jump scoring where parts overhang an edge. | Sierra Circuits |
| V-score | Cuts about one third of the thickness from each side and leaves one third. Square or rectangular boards only. | Sierra Circuits |
Panelization
Ask the assembler whether they want single boards or a panel before layout ends. Rounded wearable boards cannot be V-scored, so they use breakaway tabs. Keep traces and parts clear of tabs, as in the keep-out row above. Approve the panel drawing in writing.
Fiducials
Fiducials are bare copper marks the machine camera uses to find the board. Put global fiducials on each board and on the panel rails, and local ones next to fine-pitch parts. On a tiny board the clear area around each mark costs space, so plan for it during placement.
Part packaging and moisture
Machines feed parts from tape, reels, trays or tubes. Sierra Circuits asks for one continuous tape per line item, trays for parts that are not on tape or reel, pin 1 facing the same way throughout, and a few extra passives for attrition (Sierra Circuits kitting guide, as of November 2026). Moisture-sensitive parts also have a floor life once the bag is opened. The ESP32-S3-WROOM-1 is rated MSL 3, and its datasheet says to solder it within 168 hours of unpacking at 25±5 °C and 60%RH, or bake it first. TI points to J-STD-033 for MSL classification. This guide quotes no limits from that standard.
What fails on prototype SMT boards, and how do you catch it early?
These are common failure modes and the checks the sources point to, as of November 2026. None describes an incident at any company.
| Failure | Usual cause | Check or fix | Source |
|---|---|---|---|
| Bridging on fine-pitch QFN leads | Too much paste, or paste squeezed out by high placement force. | For 0.5 mm pitch and below, TI suggests a 20% smaller aperture when placement force is not well regulated. | Source |
| QFN floating, or opens | A 1:1 paste print on the exposed pad gives too much solder. | Print about 50% to 70% of the exposed pad area. | Source |
| Voids under the exposed pad | Air trapped in vias plugged or tented from the back, or a long soak that spends the flux before the solder melts. | Check with X-ray. TI prefers a 50% void limit in high-power parts. In TI trials, vias tented from the top gave fewer random voids. | Source |
| Tombstoning and shifted passives | Misaligned parts, from unclear outlines and centroids or mask openings that do not match pads. | Keep mask openings 1:1 with pads and include clear outlines and centroids. | Source |
| Rotated or reversed parts | Wrong rotation or units in the placement file, missing polarity marks. | Check the first article against the drawing before the batch runs. | Source |
| Module put through a second reflow | A part rated for one reflow placed on the side that goes through the oven twice. | The ESP32-S3-WROOM-1 datasheet says to solder the module in a single reflow. Put it on the side reflowed last. | Source |
A wrong rotation in the placement file repeats on every board, so check the first assembled board against the BOM and drawing before the rest runs. TI notes that IPC-A-610D, the revision its app note cites, does not require a side fillet on QFN parts, since the side terminations are not plated, and that the joint underneath is not affected when side wetting looks reduced. Confirm the rule in the current IPC-A-610 revision your assembler inspects to. This guide quotes no other criteria from IPC standards.
For how prototype builds map onto engineering gates, see EVT, DVT and PVT: what you get at each gate.
What should you ask your hardware team or assembler?
Take this list to the layout review and again before the first build order. If one shop will also program, test and box-build the device, see electronic manufacturing services (EMS) for how to choose it.
- Which stencil thickness will you use, and which part sets it?
- Have the paste layers for exposed pads been reviewed, or are they copies of copper?
- Is the reflow profile measured on this board, and which part limits the peak?
- Which parts allow only one reflow, and are they on the side reflowed last?
- Which parts are moisture sensitive, and who logs when each bag was opened?
- Will every BGA and QFN on the first boards be X-rayed, and what void limit passes?
- Who draws the panel, and does the assembler approve it?
- Who checks the first article against the BOM and drawing before the batch continues?
At Duobay, custom boards are first built in the prototype gates, and small batches of 10–1,000 units come in a later gate. See our gated prototype development process.
Questions about SMT PCB assembly
What does SMT mean on a PCB?
SMT stands for surface mount technology. Parts are soldered to pads on the board surface, usually by printing paste through a stencil and reflowing it. Through-hole parts have leads that go through drilled holes.
Do I need X-ray inspection for a prototype run?
If the board has BGA parts or QFN parts with exposed pads, AOI cannot see those joints. TI describes transmission X-ray as the usual way to inspect QFN joints and find bridging, opens and voids (TI SLUA271C, as of November 2026). On first boards, ask for X-ray of each hidden-joint part.
Can I send parts on cut tape?
Often yes. Check the assembler's rules first. AdvancedPCB asks for continuous tape with a leader of at least 6 in for parts not on a reel. Sierra Circuits asks for one continuous tape per line item with no splices (AdvancedPCB, Sierra Circuits, as of November 2026).
How could Duobay help with SMT assembly for my device?
Duobay develops custom devices with a Shenzhen engineering team, and production runs at partner shops and factories. The BOM, layout and assembly files are part of the electronics work, and source files are assigned to you at every paid gate. We do not publish prices, and initial calls are free. Tell us about your device.
If you want your BOM, layout and assembly files checked before a first SMT build, tell us about your device.
Sources. All pages accessed November 5, 2026. Fab and assembly rules are revised, so confirm current values with your shop.
- Texas Instruments, QFN and SON PCB Attachment, SLUA271C (revised December 2023) (link)
- Espressif, ESP32-S3-WROOM-1 and WROOM-1U Datasheet v1.8 (2026-03-02), section 12 (link)
- AdvancedPCB, PCB Stencils (August 19, 2026) (link)
- AdvancedPCB, Fiducials in PCB Manufacturing (March 3, 2026) (link)
- AdvancedPCB, Prototype PCB Assembly Services (link)
- Sierra Circuits, Panel Requirements for PCB Assembly (link)
- Sierra Circuits, PCB Design for Assembly Checklist (April 8, 2026) (link)
- Sierra Circuits, V-scoring (link)
- Sierra Circuits, 6 Design Mistakes That Lead to PCB Assembly Errors (September 6, 2023) (link)
- Sierra Circuits, Kitting Guidelines for PCB Assembly (link)
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