PCB Design Process: Steps From Schematic to Board

Concept render

The PCB design process runs from requirements and a block diagram, through part selection, schematic capture and review, footprints, stack-up, placement and routing, to design rule and manufacturability checks. It ends with output files, fabrication, assembly and bring-up. Each step produces files the client should receive.

PCB design is the part of electronics development that turns a circuit idea into a board a factory can build. For a connected device it also sets radio range, battery life and how the product is tested. This guide lays out the PCB design process step by step, names the IPC standards each step relies on, and lists the files you should receive at the end. It links to our detailed guides for layout, stack-up and assembly instead of repeating them.

This is an engineering summary. Fab capabilities and standard revisions change, so confirm with your fab and the current documents before you rely on any rule. All sources were read on November 12, 2026.

What are the PCB design steps for a product?

The table lists the thirteen PCB design steps a product board usually passes through and what each step should leave behind. The order is engineering practice. Real projects loop back, especially between placement and the enclosure.

Sierra Circuits, a board manufacturer, describes the same flow: functional requirements feed the schematic, stack-up design, footprint generation and layout, and the information gathered during layout feeds fabrication, assembly and test (Sierra Circuits PCB layout guide, as of November 2026).

What happens before the schematic?

The first two steps cost little and prevent most redesigns. Write down what the board must do: sensors, radios, user inputs, charging, operating temperature and the certifications the product will need. Get the enclosure outline, even as a rough model, because it fixes the board shape, connector positions and antenna location.

Then draw a block diagram. Show each main chip, the buses between them and every power rail. Add a current estimate per rail in each mode: sleep, idle, active and transmit. That table drives the regulator choice and the first battery-life estimate. For small devices, our guide to LDO vs buck converters covers the regulator side.

Part selection and the BOM

Pick the main parts against the block diagram. Check lifecycle status, second sources and package type early. A part in a fine-pitch BGA can force more layers or HDI technology. Record each choice in a draft BOM with manufacturer part numbers. Our bill of materials guide explains what a production BOM holds.

How do you go from schematic to PCB?

Schematic capture and review

The schematic is the source of truth for connections. Sierra Circuits calls schematic capture the first step for a logical PCB and suggests adding notes for the layout designer, such as which pin needs a guard trace (Sierra Circuits, as of November 2026). Mark critical nets: RF feeds, clocks, high-speed pairs and high-current paths.

Before layout, a second engineer should review the schematic against every datasheet and the chip vendor's reference design. Vendor guides often fix details such as decoupling values, strapping pin states and crystal load. For an example, see what changes when an ESP32 dev board becomes a custom PCB.

Footprints and the library

Each schematic symbol needs a footprint, and Sierra Circuits says footprints must exist before you start the layout (Sierra Circuits, as of November 2026). Footprints for surface-mount parts follow IPC-7351, Generic Requirements for Surface Mount Design and Land Patterns (IPC design standards, as of November 2026). Sierra Circuits' footprint guide adds practical checks: symmetric pads to avoid tombstoning, pin 1 indicators, a solder mask bridge typically 4 to 8 mils between pins, and pin mapping drawn from the top view (Sierra Circuits footprint guide, as of November 2026). A wrong footprint can stop a first board from working, so check each one against the part's datasheet drawing.

Stack-up

Sierra Circuits says the stack-up must be designed before layout starts (Sierra Circuits, as of November 2026). The stack-up sets layer count, copper weights and dielectric thickness, and with them the trace widths for impedance-controlled lines. Agree it with the fab you plan to use. Our guide to PCB layers and thickness covers how many layers a small device needs.

How are placement and routing done?

Placement decides most of what routing can achieve. Place the parts with no freedom first: connectors, buttons, sensors that face a window, the antenna and the battery. Sierra Circuits recommends dividing the circuit into functional blocks, such as power supply, controller and analog sensors, and placing parts in the flow of the signal (Sierra Circuits, as of November 2026). Check every placement against the enclosure model.

For routing, the same guide says to identify and route critical tracks first, keep nets short, place ground and power vias next to component pins, and use multiple vias where high current changes layers (Sierra Circuits, as of November 2026). In a wireless device, RF traces, crystal lines and fast pairs come first, then the power path. Our PCB layout guide for small devices covers ground planes, decoupling, RF and test points in detail. For via choices on dense boards, see PCB via types.

What do DRC and DFM checks catch?

Two checks come before any order. They catch different problems.

• Design rule check (DRC). Sierra Circuits describes DRC as verifying that the layout follows the constraints set in the CAD tool, such as minimum trace width and spacing, with constraints typically derived from IPC-6012, IPC-2221 and IPC-7351. The result is pass or fail (Sierra Circuits DRC vs DFM, as of November 2026).
• Design for manufacturing (DFM). DFM checks whether the board can be built reliably within the fab's capabilities and tolerances. Sierra Circuits notes a board can pass DRC and still fail in production, for example a via that meets the annular ring rule in the tool but is at risk from drill misalignment (Sierra Circuits DRC vs DFM, as of November 2026).

Sierra Circuits suggests running DFM checks during schematic, placement, routing and final approval, and updating the DRC rules to the chosen fab's capabilities once it is selected (Sierra Circuits DRC vs DFM, as of November 2026). Its layout guide gives two common rules of thumb: a pad at least 1.8 times the hole diameter, or at least 0.5 mm larger, and a 10:1 aspect ratio for through-hole vias (Sierra Circuits, as of November 2026). Your fab's own capability sheet overrides these.

Which IPC standards apply to PCB design?

IPC publishes the standards most fabs and design teams work from. The titles below are as listed on IPC's design standards page, as of November 2026 (IPC design standards). The "used for" column is our short summary.

We quote no values from these standards here. They are sold documents, and the right class and revision depend on the product. Agree with your fab and assembler which ones and which class apply.

What files go to the fab and the assembler?

The fab needs the copper, mask, legend, drill and outline data. Ucamco, which maintains the Gerber format, says Gerber layer files represent copper layers, solder mask, legend, and drill and route data, and that the Gerber job file carries fabrication characteristics such as thickness and finish. The latest specification listed on its page is revision 2024.05 (Ucamco Gerber format, as of November 2026).

Two other formats bundle more in one package. Sierra Circuits describes ODB++ as a large export with multiple data layers, and IPC-2581, also called IPC-DPMX, as a neutral XML format that holds design and manufacturing data in a single file (Sierra Circuits IPC-2581 guide, as of November 2026). Ask your fab which format it prefers.

The assembler needs the BOM, a pick-and-place file with part positions and rotations, and an assembly drawing. For how assembly runs, see SMT PCB assembly and PCB vs PCBA.

What happens at bring-up and revision?

The first boards arrive and are powered up step by step. Bring-up usually checks for shorts on each rail, then powers the board with a current limit, measures each rail, loads firmware, tests each interface and checks the radio. Every issue goes on a list for the next revision, with the fix and who approved it. After the board is in production, changes go through a formal change process. See engineering change orders. For test planning, see in-circuit test vs functional test.

The first custom board is a gate of its own in a Duobay project. The PCB prototype gate shows what it covers.

Which files should the client receive?

If someone designs a board for you, ask for these at each paid milestone. Without them, another team cannot change or rebuild the board.

• Schematic source files and a PDF of every sheet.
• PCB layout source files, including the design rules and stack-up used.
• The part library: symbols, footprints and 3D models.
• BOM with manufacturer part numbers, approved alternates and reference designators.
• Fabrication data: Gerber, ODB++ or IPC-2581, drill files and the fabrication drawing.
• Assembly data: pick-and-place file, assembly drawing and any paste or stencil notes.
• The netlist for bare board test, such as an IPC-D-356 file.
• Schematic review log, DRC report and the fab's DFM findings with how each was closed.
• Bring-up report and the list of changes for the next revision.

If you are planning a device and want the PCB designed as part of the full product, tell us about your device.

Sources. All pages accessed November 12, 2026. Fab rules vary by fab and process, so confirm current values with the fab you use.

• IPC, IPC Design Standards (titles of IPC-2221, IPC-2222, IPC-7351, IPC-2152, IPC-2141, IPC-2581, IPC-D-356) (link)
• Sierra Circuits, PCB Layout Design (link)
• Sierra Circuits, Design Rule Check vs. Design for Manufacturing (link)
• Sierra Circuits, How to Design Correct PCB Footprints (link)
• Sierra Circuits, How to Export and Get Started with IPC-2581 (link)
• Ucamco, Official Gerber Format website (link)