Concept renderStart a small connected device at four PCB layers: signal, solid ground, power, signal. Espressif recommends that build for its ESP32-S3. Two layers can work for a simple radio board with a complete ground plane. Fine-pitch BGA fan-out pushes you to six or more. Typical board thickness is 1.57 mm, and thinner boards suit wearables.
Layer count and board thickness get set early, often before anyone draws a trace. They decide which fabs can build the board, how the radio performs and what each board costs. This guide helps a product lead check a stack-up proposal. Every figure links to a chip vendor note or a fab or design-tool guide. For where the stack-up sits among the other board design steps, see the PCB design process.
This is an engineering summary. Fab limits differ between shops and change over time, so confirm every number with the fab that will build your board. We quote no threshold from paywalled IPC standards.
How many PCB layers does a small connected device need?
Count from the parts. The largest package, the radio and the number of supply rails set the floor. The table below maps common board types to a layer count, as of November 2026.
| Layers | Typical fit | What has to be true | Watch out for | Source |
|---|---|---|---|---|
| 2 layers | A simple board: one radio chip, few rails, spare room. | The bottom stays almost empty, as a complete ground plane under the chip, RF path and crystal. Espressif allows this for the ESP32-S3. | Parts on one side only, and little room for power routing. | Espressif, as of November 2026 |
| 4 layers | A BLE or Wi-Fi SoC board with sensors, a charger and a few rails. | Layer 2 is a solid ground plane with no signal traces. Power sits on layer 3. Espressif recommends this build for the ESP32-S3. | Any trace on layer 2 cuts the ground plane under the RF and crystal. | Espressif, as of November 2026 |
| 6 layers | A fine-pitch BGA processor or several high-speed lines. | TI says every connection of its 0.5 mm pitch package-on-package processor can be routed on 6 layers without via-in-pad. | In TI's first option, signal layers 1 and 2 sit side by side, as do 5 and 6. TI warns to limit crosstalk between them. | TI SPRABB3, as of November 2026 |
| 8 or more, or HDI | A large BGA with many inner ball rows, or a board too small for through-hole fan-out. | In TI's 0.5 mm pitch example, each inner row of balls past the fourth needs one more routing layer. TI notes that blind microvias open more routing channels on inner layers. | HDI boards use sequential lamination for microvias. Sierra Circuits says this adds cost and build time. | TI SPRABB3, Sierra Circuits, as of November 2026 |
If your device is built around one radio SoC like the ESP32-S3, the vendor guide points you to the first two rows. An applications processor in a fine-pitch BGA, like the one in TI's guide, puts you in the last two. If you have not chosen the processor yet, that choice may decide the board. See MCU or Linux SoC for an AI wearable.
The step from 2 to 4 layers changes how the board is made. EMA notes that single-layer and 2-layer boards cost about the same, because neither needs lamination (EMA, as of November 2026). A 4-layer board does.
What goes on each layer of a PCB stack-up?
The stack-up is the order of copper layers and the insulation between them, drawn on the fabrication drawing, as EMA describes it. Each signal layer should sit next to a plane it can reference.
Espressif's recommended 4-layer build for the ESP32-S3 is a clear example, as of November 2026 (Espressif):
- Layer 1, top: signal traces and components.
- Layer 2, ground: no signal traces, so the ground plane stays complete.
- Layer 3, power: power, with ground poured to isolate the RF and the crystal.
- Layer 4, bottom: a few signal traces.
The same guide asks for the chip's ground pad to connect to the ground plane through at least nine vias, and for the RF trace to stay on the outer layer without changing layers.
Two-layer boards
On 2 layers, the bottom becomes the ground plane. Espressif asks for no components there and as few traces as possible. Route power on the top layer, and use vias to the bottom only when you must. Every trace on the bottom cuts the plane, so a 2-layer board works only when the routing is light. For placement, ground return paths and antenna keep-outs once the layer count is set, see PCB layout rules for small battery-powered devices.
Six layers and up
TI's guide for a 0.5 mm pitch package-on-package processor lists three 6-layer stack-ups (TI SPRABB3, June 2010, read November 2026). One routes high-speed signals on layers 3 and 4, between ground and power. Another puts ground on the top layer with pad cutouts, which TI says cuts vias by about 30% and reduces EMI. The guide dates from 2010, so treat these as patterns to discuss with your fab.
What drives PCB layer count up?
These five drivers push the layer count up. The table shows each one with a sourced reason and what to check, as of November 2026.
| Driver | Why it adds layers | What to check |
|---|---|---|
| Fine-pitch BGA fan-out | Inner rows of balls need vias and their own routing layers. | Pitch and ball rows of the largest package. |
| RF and antenna | The RF trace needs a solid ground right under it, and keep-out areas take board space. | The RF reference layer and the clear area under the antenna. |
| Power rails | Wide power traces are hard to fit between dense parts on one layer. | Number of rails and the widest trace each needs. |
| High-speed interfaces | Each controlled-impedance trace needs a reference plane. TI gives 45 to 65 Ω as the usual datasheet range. | Every impedance line and the plane it references. |
| Fab rules you accept | TI notes that looser trace and space rules raise yield, but the board may get larger and need more layers. | The trace, space and via sizes your fab calls standard. |
Sources: TI SPRABB3, MacroFab BGA escape routing (August 17, 2016), Espressif ESP32-S3 layout guide, all read November 2026.
BGA and fine-pitch packages
At 0.5 mm pitch, TI fits one trace between two pads. That lets the outer two rows escape on the top layer. Inner rows need a via between the pads, and with only one trace between vias, each inner row past the fourth needs its own routing layer. A larger package with more rows needs more layers. MacroFab makes the same point: larger BGAs with more balls generally need more layers.
RF and antennas
The radio sets rules that compete for space. Espressif wants a 50 Ω trace, a complete ground plane on the adjacent layer, all layers kept clear under the IPEX antenna connector, and the module's PCB antenna at the board edge or outside it. It recommends at least 15 mm of clearance around the antenna in all directions inside the housing (Espressif, as of November 2026). For antenna types, matching networks and tuning inside the housing, see PCB antenna design for small devices. A small board loses a lot of area to these rules, and the routing they displace has to go on another layer. For trackers, the GNSS antenna adds its own rules. See GNSS antenna placement in small trackers.
Power rails
A charger, a radio, an amplifier and sensors can each need their own rail. Espressif asks for main power traces of at least 25 mil, at least 20 mil for the VDD3P3 supply at pins 2 and 3, and 10 mil for other power traces, with at least two vias where a main trace changes layers. Wide traces are hard to fit between dense parts, which is one reason a 4-layer build gives power its own layer.
What PCB thickness should you choose?
Thickness is the finished board, copper and all. It is a separate choice from layer count, but the two limit each other. The table lists the values that MacroFab and EMA publish, as of November 2026.
| Thickness | What the source says | When to use it |
|---|---|---|
| 0.79 mm (0.031 in) | One of the common thicknesses listed by MacroFab. | A thinner option for small devices. Check that your stack-up fits and that the board stays stiff enough for assembly. |
| 1.57 mm (0.062 in) | The typical thickness, per MacroFab. EMA calls 0.062 in the most common FR4 supply thickness. | The default. Choose it unless the enclosure, a connector or a stack-up gives you a reason to change. |
| 2.36 mm (0.093 in) | The other common thickness listed by MacroFab. | Choose it when stiffness or a high layer count matters more than size. |
| Custom, 0.2 to 6.3 mm | MacroFab says thickness can be set in 0.01 mm steps, and 2-layer boards can go as thin as 0.2 mm. It describes 0.13 to 0.76 mm boards as suited to wearables. | Some stack-ups and layer counts have a higher minimum thickness. A custom thickness also stops the fab from sharing a panel with other designs. |
Sources: MacroFab PCB thickness options (September 27, 2018) and EMA stack-up cost adders, read November 2026.
Let the enclosure set the thickness. Take the space the mechanical design gives the board, subtract the tallest parts on each side, and check the result against what the fab can build at your layer count. More layers in a thinner board means thinner insulation between them, which changes trace widths for controlled impedance. EMA lists the distance to the reference plane as a stack-up variable and suggests letting the fab adjust it. Have the fab confirm widths for the final stack-up before layout ends.
Copper adds to thickness too. EMA says production shops most often stock half-ounce and one-ounce copper, and gives half-ounce as about 17.78 µm (as of November 2026).
How do layer count and thickness change cost?
We publish no prices here, and the sources below describe cost only as direction. Get a quote from the fab that will build the board, as TI and EMA both advise.
- More layers cost more. Sierra Circuits says price rises with layer count and that lamination gets harder as layers are added (Sierra Circuits, as of November 2026).
- HDI costs more again. The same page says sequential lamination for microvias adds cost and build time, and that laser drilling generally costs more than mechanical drilling.
- Thick boards with small holes cost more to drill. Sierra Circuits ties a high aspect ratio to longer drill time and higher cost. It also says inner copper over half an ounce raises price.
- Tight rules cost more. TI says yields fall and costs rise as you approach a fab's limits. EMA says trace and space below the fab's usual range can bring a cost adder.
- Custom thickness can cost more at small volume. MacroFab says a custom thickness keeps your design off shared panels, so minimum area charges apply.
- Higher-temperature material costs more. EMA names laminate rated above 130 °C as the most common material cost adder.
TI adds two warnings. Lower-priced options on a quote often assume a large build, so at prototype volume they may cost the same or more. And one fab may class your design as advanced while another calls it standard, so get several quotes for the same stack-up.
What should you ask your hardware team?
Bring this list to the stack-up review before layout starts. Write down which fab confirmed each answer.
- Which part sets the layer count? Name the package, the pitch and the number of ball rows.
- Can the board be built on 4 layers with a solid ground plane on layer 2? If not, what blocks it?
- Which layer does the RF trace reference, and is the area under the antenna connector clear on every layer?
- What finished board thickness do we need, and does the stack-up for that layer count meet the fab minimum?
- Is the stack-up balanced from top to bottom, and has the fab confirmed it?
- Are we using the fab's standard trace, space and via sizes, or pushing its limits?
- Do we need microvias, and did we get several quotes with and without them, at prototype and pilot quantity?
Stack-up and thickness decisions sit inside the electronics work, before the first prototype boards are ordered. For how the electronics work is organized, see engineering.
Can a Bluetooth or Wi-Fi device use a 2-layer PCB?
It can. Espressif allows a 2-layer board for the ESP32-S3 if the bottom layer has no components, very few traces and a complete ground plane under the chip, the RF path and the crystal (Espressif, as of November 2026). It still recommends 4 layers.
Why are PCB layer counts almost always even?
As a rule, layers are added in pairs, EMA says, for example one for ground and one for power (EMA, as of November 2026). Sierra Circuits lists a balanced stack-up as a design-for-manufacture item (Sierra Circuits). Ask your fab before you plan an odd count.
Is there an official standard PCB thickness?
We did not find one in the sources we read. 1.57 mm (0.062 in) is the typical value, per MacroFab and EMA (as of November 2026). EMA points to IPC-4101 for FR4 base materials. We quote nothing from that standard.
How could Duobay help with layer count and thickness?
The stack-up is part of the electronics work our Shenzhen engineering team does on a custom device, and the source files are assigned to you at every paid gate. We do not publish prices, and initial calls are free. Tell us about your device.
If you want a layer count and thickness checked against the packages and enclosure your device needs, tell us about your device.
Sources. All pages accessed November 5, 2026. Fab limits and vendor guides are revised, so confirm current values before you decide.
- Espressif, ESP32-S3 Hardware Design Guidelines, PCB Layout Design (latest documentation) (link)
- Texas Instruments, PCB Design Guidelines for 0.5mm Package-on-Package Applications Processor, Part I, SPRABB3 (June 2010) (link)
- MacroFab, Customization Options: PCB Thickness (September 27, 2018) (link)
- MacroFab, Escaping BGAs: Methods of Routing Traces from BGA Footprints (August 17, 2016) (link)
- EMA Design Automation, Selecting a Sound PCB Stack-Up Strategy, Part 1: Cost Adders (2020) (link)
- Sierra Circuits, PCB Price Composition (link)
- Sierra Circuits, PCB Stack-Up Design Guide, summary page (link)
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