In-Circuit Test vs Functional Test: A PCB Test Plan

Illustration

An in-circuit test probes each net of an assembled board to find shorts, opens and wrong or missing parts, using a bed-of-nails fixture or flying probes. A functional test powers the board and checks that it does its job. Many teams use both: a structural check first, then a functional test on every unit.

Assembled boards fail in two different ways. Some have a build fault: a bridged pin, a missing resistor, a part turned the wrong way. Others are built correctly and still do not work, because a crystal does not start or the radio is out of tune. In-circuit test looks for the first kind. Functional test looks for the second. This guide compares the methods and shows what to plan in layout and firmware so the factory can test the boards.

Every figure links to a fab test guide, a chip vendor document or the IEEE page, as of November 2026. We quote nothing from the paid IEEE 1149.1 text.

What is an in-circuit test, and how is it different from a functional test?

An in-circuit test (ICT) checks how the board was built. Sierra Circuits calls it the bed of nails method: pre-mounted probes contact the board through preset access points, and the test checks for shorts, open circuits and missing or misplaced parts (Sierra Circuits DFT guide, as of November 2026). Because each probe sits on a known net, a failure points to a place on the board.

A functional test checks what the board does. The board is powered, runs firmware and is asked to do its job: read a sensor, write to memory, transmit, play a tone. Sierra Circuits notes that the customers or designers supply the functional test parameters, depending on the design (Sierra Circuits DFT guide, as of November 2026).

A board can pass ICT and fail functional test because of a firmware or tuning problem. It can also pass a short functional test with a weak joint that ICT would flag. So many test plans run both.

What does each PCB test method catch and miss?

The table compares four methods. Optical and X-ray inspection also catch assembly faults, and they are covered in SMT PCB assembly: steps, files and checks.

Sources: Sierra Circuits, How Flying Probe Testing Works (September 25, 2025), Sierra Circuits DFT guide (July 12, 2022) and TI SSYA002D, all as of November 2026. Rows or cells without a named source are general engineering descriptions.

Bed of nails or flying probe?

Both are in-circuit tests, and the fixture is the difference. Per Sierra Circuits, as of November 2026, ICT needs a custom bed-of-nails fixture, has a long development lead time and runs about 1 minute per board. Flying probe needs no fixture, adapts to design changes by reprogramming and runs up to 15 minutes per board. Sierra Circuits places ICT at high volume and flying probe at low volume and prototypes.

When does boundary scan (JTAG) help on a device board?

Boundary scan is defined in IEEE 1149.1, the Standard for Test Access Port and Boundary-Scan Architecture. The IEEE page lists the 2013 revision as inactive-reserved since March 21, 2024, with an active project, P1149.1, developing a new revision (IEEE SA, as of November 2026). The test bus is what most engineers call JTAG.

TI's 1997 primer, SSYA002D, explains the idea. Boundary-scan cells sit between each pin and the chip's logic, and they link into a scan path from the test data input (TDI) to the test data output (TDO). In test mode the cells drive values out of one chip and capture them at the next, which tests the wiring between them. TI notes that multilayer boards and chips with fine-pitch pins are very hard to reach with probes, and says a scan path at the chip boundary can overcome these physical access problems. The primer lists nine instructions in the standard, three of them required: BYPASS, SAMPLE/PRELOAD and EXTEST. The primer dates from 1997, so check current details against the standard.

Check the chip before you count on it

Boundary scan only reaches pins on chips that implement it. Scan tools read each chip's Boundary-Scan Description Language (BSDL) file. TI's primer says BSDL captures the essential features of a chip's IEEE 1149.1 implementation. Ask the chip vendor for the BSDL file for your exact part. A JTAG port on a microcontroller may exist for debugging and flash programming. Espressif, for example, documents the ESP32-S3 JTAG port for debugging with OpenOCD and GDB, and says the ESP32-S3 does not support SWD (ESP-IDF v6.1, as of November 2026). On a small wearable with one main chip, boundary scan may reach only a few nets. For choosing between SWD and JTAG debug ports, see SWD vs JTAG: Debug Ports, Connectors and Probes.

What should a functional test on a PCB check?

Write the functional test from the product requirements, then trim it to what a fixture can run in reasonable time. A typical list for a connected device:

• Current draw at power-on and in sleep, against limits from your power budget.
• Each regulator rail within its tolerance.
• Every sensor answers on its bus and returns a plausible reading.
• Flash or external memory passes a read and write check.
• Buttons, LEDs, microphones and speakers respond.
• Battery charging starts and stops as designed.
• The radio transmits and receives within limits.
• Firmware version and unit serial number are written and read back.

Chip vendors publish factory test methods for their radios. Espressif's production testing guide is filed under its ESP32-S3 documentation but written for its Wi-Fi products in general, with ESP32 and ESP32-S2 modules as examples. It describes a host PC that downloads test firmware into the RAM of the device under test and runs it. Its test items include a GPIO conductivity test that finds soldering defects such as solder bridges, a flash read and write test and a firmware version check. It says the RF tests must run in a shielded enclosure, and it lists V33, GND, RXD, TXD, EN and GPIO0 as the test points to connect (Espressif Production Testing Guide, as of November 2026). A GPIO conductivity test like this gives a functional test some of the fault-finding power of ICT.

Which test mix fits prototypes and small batches?

The rows below are engineering reasoning from the sources above. None describes a specific project.

Whatever the mix, run the functional test on every unit you ship. Check the first units of each lot against the drawing and BOM before the rest are built; see first article inspection. Our gated development process shows where prototype boards and small batches fall.

How do you plan test points on the PCB, programming access and test firmware?

Testability is set at layout. Once the board is routed, adding test points means a new revision.

Test points

Fixture pad sizes and spacing, one probe point per net, access from one side and untented via test points are covered in PCB layout rules for small devices. Two more ICT rules from the same Sierra Circuits guide: leave a gap of at least 5.08 mm on the four sides of each BGA, and use a doubled test point or 4-wire measurement for resistors below 100 Ω (Sierra Circuits DFT guide, as of November 2026). For flying probe, Sierra Circuits gives a 6 mil minimum test pad (20 mil recommended) and 10 to 20 mil between test points (Sierra Circuits, as of November 2026). Confirm them with your test shop.

Programming and debug access

Decide how firmware gets onto the board in the factory, then give the fixture a way to reach those pins. On the ESP32-S3, the JTAG interface connects by default to the built-in USB_SERIAL_JTAG peripheral. Using an external adapter on GPIO39 to GPIO42 needs an eFuse burned first, either DIS_USB_JTAG or STRAP_JTAG_SEL with GPIO3 choosing the interface at reset, and Espressif warns that burning eFuses is irreversible (ESP-IDF v6.1, as of November 2026). Other chips differ, so read your vendor's guide.

Security settings and test order

On the ESP32-S3, Espressif says that by default, enabling flash encryption or secure boot disables JTAG debugging. On first boot the bootloader burns an eFuse bit that disables JTAG permanently, and it cannot then be re-enabled. Espressif says the option to keep JTAG open, CONFIG_SECURE_BOOT_ALLOW_JTAG, removes all physical security (ESP-IDF v6.1, as of November 2026). Write the test order down: which tests need the debug port, when the final firmware goes on, and when the security fuses are set. Key order and signing for secure boot are covered in secure boot and signed firmware for small devices.

Test firmware

Decide early between separate test firmware and a test mode inside the product firmware. Espressif's method loads test firmware into RAM. A test mode in product firmware must be locked or removed before units ship. Either way, store results against each serial number.

What should you ask your hardware team?

Take this list to the schematic review, and again before layout is released.

• Which test method runs at each build: bench bring-up, flying probe, ICT, boundary scan, functional test?
• Does every net have a test point, or which nets are left to the functional test, and why?
• Which chips on the board support IEEE 1149.1, and do we have a BSDL file for each exact part?
• How is firmware loaded in the factory: USB, UART, JTAG or SWD? Which pins must the fixture reach?
• Does secure boot or debug lock shut the port the factory test needs? In what order are the security fuses set?
• What does the test firmware check, what are the pass limits, and who signed off on them?
• Which radio tests need a shielded box, and does the test station have one?

If you want test points, factory firmware and the test order planned as part of your device project, tell us about your device.

Sources. All pages accessed November 6, 2026. Fab rules and vendor documents are revised, so confirm current values before you decide.

• Sierra Circuits, How Flying Probe Testing Works for PCB Assembly (September 25, 2025) (link)
• Sierra Circuits, Design for Testing (DFT) Guidelines for PCB Manufacturing (July 12, 2022) (link)
• Texas Instruments, IEEE Std 1149.1 (JTAG) Testability Primer, SSYA002D (1997) (link)
• IEEE SA, IEEE 1149.1-2013, Standard for Test Access Port and Boundary-Scan Architecture (link)
• Espressif, ESP-IDF v6.1 Programming Guide, ESP32-S3 JTAG Debugging (link)
• Espressif, ESP-IDF v6.1, ESP32-S3 Configure Other JTAG Interfaces (link)
• Espressif, ESP-IDF v6.1, ESP32-S3 JTAG Tips and Quirks (link)
• Espressif, Production Testing Guide, ESP32-S3 documentation (link)