Concept renderAn HDI PCB uses laser-drilled microvias, often placed in the pad and stacked or staggered across thin build-up layers, to route more connections in a small area than through-hole vias allow. Wearables and rings use HDI to escape fine-pitch chip-scale packages on tiny boards. It adds lamination cycles, fill rules and reliability tests to plan.
A smart ring or a health band has very little board area, and the chips that fit in it often come in wafer-level packages with balls packed close together. At some point the through-hole vias on a standard board stop fitting between the pads. This guide explains the HDI terms and IPC-2226 types, when a wearable needs HDI, and what it changes for layout, the fabricator and review. It contains no Duobay price.
Figures and rules below come from the sources listed at the end, read on November 5, 2026. IPC standards are paywalled. Where we only read a public summary, we say so, and we do not quote numeric limits from the standards themselves.
What is an HDI PCB?
HDI means high density interconnect. The design standard is IPC-2226A, dated September 2017 in the table of contents and scope excerpt that IPC publishes, as of November 2026. Its scope says it covers the design of organic and inorganic HDI printed boards and structures for component mounting and interconnections (IPC-2226A table of contents). A fabricator design guide sums it up as a board with a higher wiring density per unit area than a conventional PCB (HDI design guide).
The density comes from the vias. A standard multilayer board joins layers with mechanically drilled holes that run through the whole board. An HDI board adds thin build-up layers joined by small laser-drilled microvias, so a connection only uses the layers it needs. For through, blind and buried vias and how they compare, see our guide to PCB via types. Key terms for HDI, as of November 2026:
| Term | What it means | Source |
|---|---|---|
| Microvia | A small plated hole that connects adjacent layers. One fabricator glossary gives a size range of 100 to 150 µm and a typical aspect ratio of 0.75:1. | Fabricator glossary |
| Via-in-pad | A microvia placed inside a component land. The fabricator design guide says microvias should be filled or capped for a planar copper surface. | Fabricator HDI guide |
| Stacked microvias | Microvias built directly on top of each other. The fabricator guide says stacked vias are filled with electroplated copper. | Fabricator stacked and staggered guide |
| Staggered microvias | Microvias on different layers, offset from each other so they do not touch. The same guide prefers staggered over stacked when you connect more than 2 layers. | Fabricator stacked and staggered guide |
| Any-layer (ELIC) | Conductors on any layer can be joined freely with copper-filled stacked microvias. The guide says this is used for complex, large pin-count parts. | Fabricator HDI guide |
Which HDI structures and IPC-2226 types should you know?
You will see two ways to describe an HDI build. Fabricators often use build-up notation. Designers and spec writers may use IPC-2226 type numbers. Both describe how many microvia layers sit on each side of the core.
Build-up notation
The notation counts microvia layers on each side of a core of n layers. One PCB supplier summary gives 1+n+1 as a single layer of microvia, 2+n+2 as two layers and 3+n+3 as three layers, as of November 2026 (HDI types summary). A board written 2+6+2 has two build-up layers on each side of a six-layer core.
IPC-2226 types
The table below follows the same supplier summary of IPC-2226 Types I to III, as of November 2026. We did not read the standard itself, which is paywalled, so check the current edition before you write a type into a contract.
| Type | Build-up notation | Construction |
|---|---|---|
| Type I | 1+n+1 (or one side only) | A single microvia layer on one or both sides of the core. Plated microvias plus through holes. Blind vias, no buried vias. |
| Type II | 1+n+1 (or one side only) | A single microvia layer on one or both sides of the core. Plated microvias plus through holes. Blind and buried vias. |
| Type III | 2+n+2 or more | At least two microvia layers on one or both sides of the core. Plated microvias plus through holes. Blind and buried vias. |
Source: PCB supplier summary of IPC-2226 types, as of November 2026. The summary covers only Types I to III. Any-layer builds are described in the fabricator HDI guide.
When does a wearable need HDI?
Wearables push toward HDI for one reason: small chip packages on a small board. TI, for example, offers its wafer-level DSBGA packages at 0.3, 0.35, 0.4 and 0.5 mm ball pitch, as of November 2026 (TI AN-1112). A package that small leaves little room between balls for traces, and inner balls may have no path out on the top layer.
Pitch alone does not decide it. Ball count, rows in use and the board outline all matter. The real test is to draw the escape for your densest part before you choose the stackup. Use this table as a starting point for that conversation. Where a row rests on a source, it says so. The rest is our engineering reasoning.
| What you find | Typical next step | What to watch |
|---|---|---|
| The board fits with through-hole vias at your outline | Stay with a standard multilayer board. | Fewer lamination cycles and fewer fab rules to confirm. |
| A fine-pitch chip-scale part cannot escape its inner balls with through-hole vias | Start with one microvia layer per side (1+n+1). | Draw the escape first. Count which ball rows need a via in or next to the pad. |
| One microvia layer still cannot escape the package, or you run out of routing layers under it | Move to two or more build-up layers (2+n+2) and choose stacked or staggered vias. | Staggered is preferred for spans of more than 2 layers in the fabricator guide we read. Stacked saves space but needs copper fill. |
| Several high-pin-count parts share a very small board | Ask the fabricator about any-layer (ELIC) construction. | Any layer can be joined to any other with stacked, copper-filled microvias, so fill and reliability evidence matter most here. |
The processor package drives the board too, so check it before you lock the chip. Our guide on MCU versus Linux SoC for AI wearables covers the processor side.
What does HDI PCB design change in the layout?
HDI PCB design follows the chip vendor's land pattern rules and the fabricator's drill rules together. The rows below come from TI's application note for its wafer-level packages (SNVA009AI, revised December 2019) and from one fabricator's HDI guides, all as of November 2026. Your own chip vendor and fabricator numbers win for your board.
| Topic | Rule in the source | Source |
|---|---|---|
| Pad definition | Use non-solder-mask-defined (NSMD) pads for via-in-pad microvias. TI says NSMD gives adequate wetting area on the copper pad. | TI AN-1112, as of November 2026 |
| Trace width at the pad | For NSMD pads, the trace at the land should not exceed 2/3 of the pad diameter. | TI AN-1112, as of November 2026 |
| Copper weight | TI recommends less than 1 oz copper for higher solder joint stand-off on its wafer-level parts. | TI AN-1112, as of November 2026 |
| Microvia wall | TI recommends a microvia wall thickness of at least 15 µm, and offset vias when microvias are needed for routing. | TI AN-1112, as of November 2026 |
| Surface finish | OSP or ENIG is preferred. For ENIG, gold must be less than 0.2 µm thick. HASL is not recommended. | TI AN-1112, as of November 2026 |
| Aspect ratio | Microvias generally have an aspect ratio below 1, with 0.75:1 given as ideal by the fabricator guide. | Fabricator guide, as of November 2026 |
| Drill-to-copper clearance | A typical value is 7 to 8 mil. The guide notes that design tools do not check this, so take the number from your fabricator. | Fabricator guide, as of November 2026 |
| Staggered spacing | For staggered vias, keep the separation between via centers greater than the microvia diameter. | Fabricator guide, as of November 2026 |
Two points follow. First, via-in-pad changes the fab drawing. The fabricator guide says microvias should be filled or capped for a planar copper surface, and the IPC-4761 section below lists dimples and trapped air as risks. The drawing must say which pads are filled and capped. Second, the stackup becomes a design input. Dielectric thickness sets the microvia depth, and depth over diameter sets the aspect ratio. Agree it with the fabricator before routing starts.
What should you confirm with the fabricator?
HDI capability varies by shop and by line. Settle these points in writing before layout, and keep the replies with the design files.
| Item | What to get from the fabricator |
|---|---|
| Smallest laser microvia and its capture pad | Their capability sheet, in writing, for the dielectric thickness you plan to use. |
| Maximum microvia aspect ratio they will build | A number they will hold on your stackup. Compare it with the 0.75:1 ideal in the guide we cite. |
| Stacked microvia limit | How many microvias they stack, and whether they require copper fill for each level. |
| Via-in-pad fill and cap | Which IPC-4761 type they build for via-in-pad (Type VII is filled and capped), the fill material and how they control dimples. |
| Lamination cycles | How many sequential laminations your stackup needs, and how that changes lead time on their line. |
| Reliability test method | Whether they run electrical-resistance test coupons through reflow simulation, and which coupon design they use. |
| Acceptance class and spec edition | Which IPC-6012 edition and class your purchase order names. Ask them to confirm the current edition. |
Via fill and cap: IPC-4761
IPC-4761 is the design guide for protecting via structures. A fabricator via-filling guide describes Type VII as a filled via capped with a secondary metalized coating on both sides, mostly used for via-in-pad and stacked microvias in HDI boards, as of November 2026 (via filling guide). The same guide lists the concerns: adhesion between the metal coating, the fill and the copper pad, and dimples on the surface when the via is not fully filled or the coating is thin. Air trapped in those dimples can cause problems during assembly. Ask how your fabricator controls each one.
Microvia reliability evidence
On March 6, 2019, IPC issued an industry warning on microvia reliability. Citing an IPC white paper on stacked microvias, it tied the failures to a weak interface between microvia target pads and electrolytic copper fill. It said these failures typically occur during reflow but are often undetectable at room temperature. It said thermally stressed microsections and light microscopes alone are no longer effective for finding these failures, and pointed to coupons that measure electrical resistance, such as the IPC-2221B Appendix D coupon (IPC release, as of November 2026).
On October 18, 2023, IPC released IPC-6012F, which it says incorporates test coupon designs suited to evaluate complex, interconnected via structures as part of an effort to address microvia reliability (IPC release, as of November 2026). We did not read the specification itself, so we do not quote its pass limits. Ask your fabricator which coupon and method they run, and what the result was on your stackup.
For a wearable, a latent via crack is a field failure that shows up after units ship. Plan the coupon results into the prototype builds, the way you plan the other evidence in EVT, DVT and PVT.
What should you ask in an HDI design review?
Take this list to your designer and your fabricator. Each question has an answer you can write down.
- Which parts on the BOM force HDI, and has someone drawn the escape for each one?
- Is the HDI type written the same way on the drawing and in the fabricator quote?
- Where do we use stacked microvias, where staggered, and why?
- Which pads have vias in them, and does the fab drawing call out filled and capped?
- Did we use the chip vendor land pattern and its notes on pad definition, copper weight and finish?
- Did the fabricator review the stackup and drill table before layout started, and do we have the reply in writing?
- How many lamination cycles does the stackup need, and does the schedule allow for them?
- What reliability coupons ship with each lot, and who reads the results?
- Do we receive the native layout, stackup and fab drawing as source files?
For how the electronics work fits with firmware, mechanical and test, see how our engineering is organized.
What else do teams ask about HDI PCB design?
What does HDI stand for in PCB design?
HDI stands for high density interconnect. The design standard is IPC-2226A, as of November 2026 (IPC-2226A table of contents). Its full text is paywalled, so this article quotes no numeric rules from it.
Are stacked microvias less reliable than staggered ones?
One fabricator guide prefers staggered vias when you connect more than 2 layers and says stacked vias are filled with electroplated copper (guide, as of November 2026). In 2019, IPC warned of stacked microvia failures linked to a weak interface between target pads and copper fill (IPC release). Ask your fabricator for coupon test data on your stackup.
Does every smart ring or band need an HDI PCB?
No. HDI is needed when a part cannot be routed out with through-hole vias in the space you have. Draw the escape for your densest package first. If a standard multilayer board fits, it has fewer fab steps to confirm.
Can a microsection prove that our microvias are good?
IPC said in its March 6, 2019 warning that thermally stressed microsections and light microscopes alone are no longer an effective quality tool for finding microvia-to-target plating failures. It pointed to performance-based coupons that measure electrical resistance (IPC release, as of November 2026).
How could Duobay help with an HDI board for a wearable?
Our Shenzhen electrical engineers work on the board as part of the device. In a Gate 0 feasibility study we can check whether your part list pushes you into HDI and list the fab questions to settle first. The layout and fab files are yours at every paid gate. Tell us about your device.
Which sources does this guide use?
All pages accessed November 5, 2026. Standards and capability sheets change, so re-read them before you rely on any figure.
- IPC, IPC-2226A, Sectional Design Standard for High Density Interconnect (HDI) Printed Boards, table of contents with scope and date: https://www.electronics.org/TOC/IPC-2226A.pdf (accessed 2026-11-05)
- PCB supplier summary of IPC-2226 HDI types and build-up notation: https://www.ncabgroup.com/faq/are-there-different-types-of-hdi-features/ (accessed 2026-11-05)
- Fabricator guide, Design for HDI PCB: https://www.protoexpress.com/pcb/learn-pcb/design-for-hdi-pcb/ (accessed 2026-11-05)
- Fabricator guide, staggered and stacked vias: https://www.protoexpress.com/blog/design-manufacture-staggered-and-stacked-vias/ (accessed 2026-11-05)
- Fabricator glossary, microvias: https://sierraconnect.protoexpress.com/t/pcb-glossary-microvias/3143 (accessed 2026-11-05)
- Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009AI): https://www.ti.com/lit/an/snva009ag/snva009ag.pdf (accessed 2026-11-05)
- Fabricator guide, via filling techniques and IPC-4761 types: https://www.protoexpress.com/blog/via-filling-techniques-designers-need-to-know-for-pcb-fabrication (accessed 2026-11-05)
- IPC, warning on printed board microvia reliability, March 6, 2019: https://www.electronics.org/news-release/ipc-issues-electronics-industry-warning-printed-board-microvia-reliability-high (accessed 2026-11-05)
- IPC, release of IPC-6012F, October 18, 2023: https://www.electronics.org/news-release/ipc-releases-ipc-6012f-qualification-and-performance-specification-rigid-printed (accessed 2026-11-05)
If your device has a dense board and you want the stackup and fab questions settled before layout, tell us about your device.
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