ESD Protection Design: Choosing TVS Diodes

Concept render

ESD protection keeps a static discharge from a user's finger out of the chips on your board. On a small device, that means a TVS diode at each exposed connector, contact and button, chosen for standoff voltage, clamping voltage and capacitance, placed at the entry point with a short path to ground, plus enclosure gaps and firmware that recovers.

A wearable or handheld meets static every day, and most of it lands on the parts a user touches: the USB port, the charging pins, a button, a seam. ESD protection is the design work that sends that current to ground before it reaches a chip. This guide covers where to put protection, how to choose a TVS diode for each kind of line from real datasheets, and how layout and grounding decide whether it works. For the test itself, levels and pass criteria, read ESD testing to IEC 61000-4-2.

This is an engineering summary. Part numbers are examples from Texas Instruments datasheets, not recommendations, and other vendors make equivalent parts. All sources were read on November 12, 2026.

What does ESD protection have to do in a small device?

System-level ESD is a short, fast pulse from a person into a finished, powered product. The reference test is IEC 61000-4-2. The current edition is 3.0, published March 7, 2025, and it replaced the 2008 edition. The IEC page says product committees remain responsible for choosing the tests and severity levels for their equipment. It also says the standard is not intended for characterizing the performance of ESD protection circuits (IEC 61000-4-2:2025 catalog page, as of November 2026).

That last point matters when you read datasheets. A TVS rated ±25 kV contact tells you the diode survives that strike on a test board. It does not tell you what your product does with the diode on your board, in your enclosure. Protection is a system: the part, its placement, the ground path, the case and the firmware.

A useful design goal has three parts. The discharge current takes a short path to ground. The voltage left on each protected pin stays below what that pin survives. And the firmware recovers from any upset that still gets through.

Which ESD protection diode fits each kind of line?

Start with a list of every point a user can touch, then sort the lines behind them by type. Each type pulls the choice in a different direction. The examples are TI parts with values from their datasheets, as of November 2026. The middle column and the last row are engineering reasoning.

The spread is wide. Capacitance runs from about 0.2 pF on the RF part to 105 pF on the VBUS part, because the two lines need opposite things. A fast data line or an antenna cannot carry much capacitance. A power line can, and it needs a part that survives surge energy as well as ESD.

A worked VBUS example

The TVS2200 datasheet walks through a USB Type-C VBUS input with a nominal 20 V and a required withstand of 22 V. In its example the protected port controller is exposed to a maximum of 27.1 V during surge pulses (TI TVS2200 datasheet, as of November 2026). The method carries over to any power input: start from the highest normal voltage, pick a standoff above it, then check that the clamp stays below the absolute maximum of the chip behind it.

How do you read a TVS diode datasheet?

Five numbers do most of the work.

• Reverse standoff voltage (VRWM). The highest voltage the diode holds off with low leakage. It must sit above the line's highest normal voltage. The TPD2E2U06 lists 5.5 V at under 10 µA (TI TPD2E2U06, as of November 2026).
• Breakdown voltage. Where the diode starts to conduct. The same part lists 6.5 V minimum DC breakdown.
• Clamping voltage. The voltage left on the line while the diode carries current. This is what your chip sees. Datasheets state it at a test current and pulse type, such as 1 A on a TLP pulse or 1 A at 8/20 µs, so compare parts at the same condition.
• Dynamic resistance (RDYN). How much the clamp rises as current rises. The TPD2E2U06 lists 0.5 Ω IO to ground in its DRL package, and the TPD1E10B06 lists 0.4 Ω typical (TI TPD1E10B06, as of November 2026). Lower keeps the clamp lower at the high currents of a real strike.
• Capacitance. The load the diode adds to the line in normal use. Count it in the signal budget for USB, high-speed serial and RF lines.

Unidirectional and bidirectional parts

A unidirectional part clamps a negative strike near ground and a positive strike at its clamping voltage. The TPD2E2U06 shows this: 9.7 V IO to ground and 1.9 V ground to IO at 1 A (TLP) (TI, as of November 2026). A bidirectional part, like the back-to-back TPD1E10B06, lets the signal swing both ways. Use it on audio and on any line that goes below ground in normal use.

What does an ESD protection circuit look like on the board?

The basic circuit is a TVS from the line to ground, right at the connector. Two additions are common, and both are engineering reasoning to verify on your board.

• A series element after the TVS. A small resistor or ferrite bead between the TVS and the chip slows the residual pulse and limits current into the chip's own protection. Check it against the signal's speed and drive strength.
• Filtering on slow inputs. A button or switch line can take an RC filter, which also helps with false presses after a strike. Firmware debounce adds a second layer.

Arrays save space. The TPD2E2U06 covers two lines in a 1.60 mm × 1.20 mm SOT package, and the TPDxE05U06 family comes in one-, four- and six-channel versions (TI datasheets, as of November 2026). On a crowded wearable board, a single array at the connector is often easier to route than several single diodes.

How do layout and grounding decide whether ESD protection works?

TI's ESD layout guide gives the rules (TI SLVA680, as of November 2026):

• Route from the entry point to the TVS without changing layers. If a via sits between the connector and the TVS, the strike can split and part of it reaches the protected chip through the via's inductance.
• Keep unprotected lines away from the protected trace and from any via it uses, on every layer the via crosses.
• Give the TVS a ground plane. A chassis ground connection, such as a grounded through-hole for a chassis screw, next to the TVS ground and the connector shield keeps ground shifts at the protected chips low.
• If the product has no chassis ground, tightly coupled ground planes on several layers help instead.

Small battery products rarely have a chassis, so the plane does the work. Keep the TVS ground on the main plane with short, wide connections, and keep sensitive chips away from the connector edge. For general layout rules on small boards, see PCB layout for small battery-powered devices.

The enclosure and the firmware

Plastic cases still let sparks in through seams, screw holes, light pipes and ports. Keep copper back from those openings or add insulation, and plan this before tooling. Then assume some strikes will upset the electronics anyway: a watchdog that always runs, inputs that are read more than once, and protocols that retry. The ESD testing guide covers the result classes a lab uses to judge that recovery.

ESD protection checklist for your hardware team

Bring this list to the schematic review and again to the layout review.

• Have we listed every connector, contact, button, seam and opening a user can touch?
• For each exposed line, which TVS is fitted, and what are its standoff voltage, clamping voltage and capacitance?
• Is each standoff voltage above the highest voltage the line sees in normal use, including chargers and USB PD?
• Are clamping voltages compared at the same test condition, and are they below what the protected pin survives?
• Does the antenna feed have a TVS, and did the RF team accept its capacitance and the match change?
• Is each TVS at the entry point, with no via or stub between the connector and the diode?
• Where does the TVS ground go, and how short is that path?
• Which seams and openings sit near copper, and what keeps a spark out?
• What does the firmware do after an upset, and does the device recover without the user?

ESD design is part of the engineering gates. For how those reviews are organized, see how the engineering gates run.

If you want ESD protection planned into the schematic, layout and enclosure from the first board, tell us about your device.

Sources. All pages accessed November 12, 2026. Datasheets are revised, so confirm values on the current revision before you order parts.

• IEC, IEC 61000-4-2:2025 catalog page (link)
• Texas Instruments, TPD2E2U06 datasheet, SLLSEG9C, revised December 2019 (link)
• Texas Instruments, TPD1E10B06 datasheet, SLLSEB1G, revised August 2024 (link)
• Texas Instruments, TPDxE05U06 datasheet, SLVSBO7O, revised August 2024 (link)
• Texas Instruments, TPD1E01B04 datasheet, SLVSDG3C, revised December 2016 (link)
• Texas Instruments, TVS2200 datasheet, SLVSED5C, revised August 2023 (link)
• Texas Instruments, ESD Protection Layout Guide, SLVA680 (link)